Pinned Repositories
AVrecordeR
Audio and video recording using Python
axi
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
axi_mem_if
Simple single-port AXI memory interface
common_cells
Common SystemVerilog components
common_verification
SystemVerilog modules and classes commonly used for verification
edalize
An abstraction library for interfacing EDA tools
fusesoc
Package manager and build abstraction tool for FPGA/ASIC development
gpu-short-course
nopywer
power grid design and analysis tools from geographic data with python and QGIS
vfinel.github.io
this the source code for the page https://vfinel.github.io/
vfinel's Repositories
vfinel/nopywer
power grid design and analysis tools from geographic data with python and QGIS
vfinel/AVrecordeR
Audio and video recording using Python
vfinel/axi
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
vfinel/axi_mem_if
Simple single-port AXI memory interface
vfinel/common_cells
Common SystemVerilog components
vfinel/common_verification
SystemVerilog modules and classes commonly used for verification
vfinel/edalize
An abstraction library for interfacing EDA tools
vfinel/fusesoc
Package manager and build abstraction tool for FPGA/ASIC development
vfinel/gpu-short-course
vfinel/vfinel.github.io
this the source code for the page https://vfinel.github.io/