Pinned Repositories
axi
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
axi_mem_if
Simple single-port AXI memory interface
common_cells
Common SystemVerilog components
common_verification
SystemVerilog modules and classes commonly used for verification
edalize
An abstraction library for interfacing EDA tools
fusesoc
Package manager and build abstraction tool for FPGA/ASIC development
nopywer
Analyse power grid stuff from QGIS data
vfinel's Repositories
vfinel/nopywer
Analyse power grid stuff from QGIS data
vfinel/axi
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
vfinel/axi_mem_if
Simple single-port AXI memory interface
vfinel/common_cells
Common SystemVerilog components
vfinel/common_verification
SystemVerilog modules and classes commonly used for verification
vfinel/edalize
An abstraction library for interfacing EDA tools
vfinel/fusesoc
Package manager and build abstraction tool for FPGA/ASIC development