Pinned Repositories
simcommand
SimCommand is a library for writing high-performance RTL testbenches with simulation threads in Scala using chiseltest.
tidalsim
Multi-level, sampled simulation using spike/uArch models/RTL for low latency, high fidelity, high throughput simulations
verif
dotfiles
My dotfiles, managed using chezmoi
ee227a
Files for EE227AT - Optimization Models and Applications
forex-backtester-python
An application to backtest basic trading strategies for the FX market, based on historical data.
hw-coverage-viewer
Vue app to view RTL-level coverage
publications
All my HTML posters + slides, workshop / conference papers
research-notes
Markdown notes for all ongoing research / infra projects
today
Today: A File-Centric Task Management System
vighneshiyer's Repositories
vighneshiyer/ee227a
Files for EE227AT - Optimization Models and Applications
vighneshiyer/publications
All my HTML posters + slides, workshop / conference papers
vighneshiyer/hw-coverage-viewer
Vue app to view RTL-level coverage
vighneshiyer/research-notes
Markdown notes for all ongoing research / infra projects
vighneshiyer/scala-sketch
Can we build a manual (not constraint-based), programmatic diagramming API that directly emits SVGs?
vighneshiyer/cov-proxy-model
Building a coverage proxy model with riscv-dv and RTL simulations of Rocket
vighneshiyer/spec-mining
Python library to mine LTL properties on VCD waveforms
vighneshiyer/dotfiles
My dotfiles, managed using chezmoi
vighneshiyer/today
Today: A File-Centric Task Management System
vighneshiyer/290c-hw4ml-project
EE290C (HW for ML)
vighneshiyer/academic-poster-template
An HTML+CSS template for making more accessible posters
vighneshiyer/bwrc-latex-poster-template
A latex beamerposter template for Berkeley Wireless Research Center branded posters
vighneshiyer/chisel-play
Random Chisel/Verilog stuff for undergrads to look at
vighneshiyer/chisel-sequences
sequence prototype
vighneshiyer/dotfiles-old
My dotfiles; use stow to install.
vighneshiyer/ee219c-formal
HW/Experiments for EE219C: Formal Methods
vighneshiyer/ee240b
Notes/lectures/HW/projects/playground for EE240B (Advanced Analog Circuits)
vighneshiyer/ee240b-project
EE 240B (Advanced Analog Circuits) Project
vighneshiyer/ee240c
EE 240C (Analog Interface Circuits)
vighneshiyer/ee290c-dsp
Files for EE290C (Fall 2018 - VLSI Signal Processing)
vighneshiyer/firrtl
Flexible Intermediate Representation for RTL
vighneshiyer/hammer-sandbox
A repo that contains a minimal build of hammer and plugins to run an RTL -> GDS flow (superceded by ucb-bar/hammer/e2e)
vighneshiyer/learning-rust
Just playing around
vighneshiyer/oscar22_poster
Poster for OSCAR workshop (at ISCA) - 2022
vighneshiyer/riscv-mini
Simple RISC-V 3-stage Pipeline in Chisel
vighneshiyer/simcommand-old
vighneshiyer/toy-scala-hdl
A tree-like / graph-native HDL API embedded in Scala
vighneshiyer/verilator-tristate-bug
Investigating internal tristates not working in Verilator v4.224
vighneshiyer/vighneshiyer.com
The sources of my professional website
vighneshiyer/vighneshiyer.github.io