Pinned Repositories
SAT
AES128
Hardware Accelerator for AES 128-bit Encryption and Decryption implemented (in Verilog) in Altera's FPGA board.
CRC32
32-bit CRC Hardware Accelerator and Custom Instructions implemented (in Verilog) in Altera's FPGA board.
GPU
ECE 695 Course at Purdue (CUDA)
Parallel-Programming
ECE 563 Course at PURDUE.
SAT
SAT-solver
The SAT solver checks if the given CNF formula evaluates to true for some arbitrary input combinations.
vignesh-raghavan's Repositories
vignesh-raghavan/AES128
Hardware Accelerator for AES 128-bit Encryption and Decryption implemented (in Verilog) in Altera's FPGA board.
vignesh-raghavan/CRC32
32-bit CRC Hardware Accelerator and Custom Instructions implemented (in Verilog) in Altera's FPGA board.
vignesh-raghavan/GPU
ECE 695 Course at Purdue (CUDA)
vignesh-raghavan/SAT-solver
The SAT solver checks if the given CNF formula evaluates to true for some arbitrary input combinations.
vignesh-raghavan/Parallel-Programming
ECE 563 Course at PURDUE.
vignesh-raghavan/SAT