Pinned Repositories
AES128_GFMPW0
AES128 design submission for GF180 MPW0 Shuttle
caravel-gf180mcu
This repository is the GF180MCU port of Caravel. For more information about Caravel, see the original repo at https://github.com/efabless/caravel.
DAC-2020-Tutorial
Material for OpenROAD Tutorial at DAC 2020
DSP_DAC_GFMPW0
DSP Processor for GF180 MPW shuttle
graphics_controller
graphics_controller_resubmit
MPW7 resubmission
junga_soc_mpw4
OpenROAD
OpenROAD's unified application implementing an RTL-to-GDS Flow
OpenROAD-flow-scripts
Verilog_RTL
RTL Design using Verilog Hardware Description Language
vijayank88's Repositories
vijayank88/graphics_controller
vijayank88/OpenROAD-flow-scripts
vijayank88/OpenROAD
OpenROAD's unified application implementing an RTL-to-GDS Flow
vijayank88/Verilog_RTL
RTL Design using Verilog Hardware Description Language
vijayank88/AES128_GFMPW0
AES128 design submission for GF180 MPW0 Shuttle
vijayank88/caravel-gf180mcu
This repository is the GF180MCU port of Caravel. For more information about Caravel, see the original repo at https://github.com/efabless/caravel.
vijayank88/DAC-2020-Tutorial
Material for OpenROAD Tutorial at DAC 2020
vijayank88/DSP_DAC_GFMPW0
DSP Processor for GF180 MPW shuttle
vijayank88/graphics_controller_resubmit
MPW7 resubmission
vijayank88/junga_soc_mpw4
vijayank88/open_pdks
PDK installer for open-source EDA tools and toolchains. Distributed with a setup for the Google/SkyWater 130nm process.
vijayank88/OpenLane
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.
vijayank88/magic-inverter
an inverter drawn in magic with makefile to simulate
vijayank88/OpenLane-MPW-CI
vijayank88/OpenRAM
An open-source static random access memory (SRAM) compiler.
vijayank88/openroad_useful_scripts
vijayank88/RISCV_Based_BMS
vijayank88/tt04-arbiterpuf
Submission template for Tiny Tapeout 04
vijayank88/vijayank88
Config files for my GitHub profile.