vincentchu12

Pinned Repositories

VerilogUARTModule
Verilog UART Module with Tx/Rx Fifo, supports up to 115200 bps
Language:HTML20
MotherboardSampleProject
Language:Verilog12
PiedPiper
CMPE152 Project
Language:C++10
CanvasGrades
Canvas Grade Calculator
Language:Python00
CMPE127-Toolkit
Language:Verilog00
cmpe130_group1_spam_classifier
SJSU CMPE 130: Section 6
Language:Jupyter Notebook00
CMPE131_MEEP_2
SJSU CMPE 131: Deliverables
00
Motherboard
Language:Verilog00
ostep-projects
Projects for an undergraduate OS course
Language:C00
redis-globals
Redis Wrapper for redis data types
00

vincentchu12's Repositories

vincentchu12/SmartThingsPublic
SmartThings open-source DeviceTypeHandlers and SmartApps code
vincentchu12/redis-globals
Redis Wrapper for redis data types
vincentchu12/ostep-projects
Projects for an undergraduate OS course
Language:C
vincentchu12/PiedPiper
CMPE152 Project
Language:C++1
vincentchu12/Motherboard
Language:Verilog
vincentchu12/VerilogUARTModule
Verilog UART Module with Tx/Rx Fifo, supports up to 115200 bps
Language:HTML2
vincentchu12/MotherboardSampleProject
Language:Verilog12
vincentchu12/CMPE127-Toolkit
Language:Verilog
vincentchu12/CanvasGrades
Canvas Grade Calculator
Language:Python
vincentchu12/CMPE131_MEEP_2
SJSU CMPE 131: Deliverables
vincentchu12/cmpe130_group1_spam_classifier
SJSU CMPE 130: Section 6
Language:Jupyter Notebook
vincentchu12/tutorials
Language:Jupyter Notebook
vincentchu12/vincentchu12.github.io
Language:HTML