Pinned Repositories
1st-CLaaS
Framework for developing and deploying FPGA logic in the cloud as a microservice for web and cloud applications
a2o
bextdep
Reference Hardware Implementations of Bit Extract/Deposit Instructions
Bluespec_BSV_Tutorial
Bluespec BSV HLHDL tutorial
darkriscv
opensouce RISC-V implemented from scratch in one night!
DNN_TL-V
riscv-bitmanip
Working draft of the proposed RISC-V Bitmanipulation extension
riscv-formal
RISC-V Formal Verification Framework
warp-v
WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.
vineetjain07's Repositories
vineetjain07/DNN_TL-V
vineetjain07/warp-v
WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.
vineetjain07/riscv-bitmanip
Working draft of the proposed RISC-V Bitmanipulation extension
vineetjain07/1st-CLaaS
Framework for developing and deploying FPGA logic in the cloud as a microservice for web and cloud applications
vineetjain07/a2o
vineetjain07/bextdep
Reference Hardware Implementations of Bit Extract/Deposit Instructions
vineetjain07/Bluespec_BSV_Tutorial
Bluespec BSV HLHDL tutorial
vineetjain07/darkriscv
opensouce RISC-V implemented from scratch in one night!
vineetjain07/riscv-formal
RISC-V Formal Verification Framework
vineetjain07/deep-learning-keras-tf-tutorial
Learn deep learning with tensorflow2.0, keras and python through this comprehensive deep learning tutorial series. Learn deep learning from scratch. Deep learning series for beginners. Tensorflow tutorials, tensorflow 2.0 tutorial. deep learning tutorial python.
vineetjain07/EmbeddedLinuxBBB
vineetjain07/getting-started-FV
vineetjain07/GitHubGraduation-2021
Join the GitHub Graduation Yearbook and "walk the stage" on June 5.
vineetjain07/ibex
Ibex is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, previously known as zero-riscy.
vineetjain07/LF-Building-a-RISC-V-CPU-Core
vineetjain07/NCGPythonCocotb
Written test for Python + Cocotb QC developer
vineetjain07/nexys4ddr
Various projects for the Nexys4DDR board from Digilent
vineetjain07/picorv32
PicoRV32 - A Size-Optimized RISC-V CPU
vineetjain07/pulpino
An open-source microcontroller system based on RISC-V
vineetjain07/python-cheatsheet
Comprehensive Python Cheatsheet
vineetjain07/riscv-compliance
vineetjain07/siliconcompiler
SiliconCompiler is an open source build system that automates translation from source code to silicon.
vineetjain07/tlv_flow_lib
Generic transaction flow components (like FIFOs, arbitors, and stall pipelines) for Transaction-Level Verilog
vineetjain07/VerilogBoy
A Pi emulating a GameBoy sounds cheap. What about an FPGA?
vineetjain07/warp-v_includes
A companion to /warp-v containing files that are included from /warp-v.