VHDL-SPI Protocol
Author: Vinícius Camozzato Vaz
Professor: Marcelo Berejuck
Develop a system consisting of two state machines, a BCD converter for seven segments, and four sliders as shown in Figure below. The two machines are communicate over an SPI synchronous serial bus, where a machine is master on the communication and the other is slave.
The goal is to “type” a binary number into the sliders, the Master machine sends this number via the SPI bus and the slave machine sends the received number to the seven segments (via BCD converter). The MISO wire will not be implemented.
The master sends data over the serial clock rising edge and the slave responds at the falling edge
We used Altera Quartus and Model Sim to development and tests.
If you want to create your own project with this files you should follow this steps:
1. Open Quartus
2. Create New Project
3. Add all files to your Project
4. Set SPI as Top Level Entity
Name: EP3C16F484C6
Device Family: Cyclone III
Package: FBGA
Pin Count: 484
Speed Grade: 6
Name: EP3C16F484C6
Top Level Master Simulation
Top Level Slave Simulation
Top Level SPI
You can find the Diagrams and Documentation on this link: Documentation
Pull requests are welcome. For major changes, please open an issue or send to me an email to discuss what you would like to change.