vinodganesan

hwcostmodels.github.io

FuSeConv

Code for paper "FuSeConv Fully Separable Convolutions for Fast Inference on Systolic Arrays" published at DATE 2021

Generalizable-DNN-cost-models

The codebase for "A Case for Generalizable DNN Cost Models for Mobile Devices" published at IISWC 2020

SHAKTIMAAN

SHAKTI Multiply-And-Accumulate Accelerator Network (SHAKTIMAAN), IITM's Deep Learning accelerator effort

SuperShaper

CompilerGym

A reinforcement learning toolkit for compiler optimizations

DAA

Practice codes for DAA course

git-flight-rules

Flight rules for git

GSM

Gate-Shift Networks for Video Action Recognition

hardware-aware-transformers

[ACL 2020] HAT: Hardware-Aware Transformers for Efficient Natural Language Processing

vinodganesan/CompilerGym

A reinforcement learning toolkit for compiler optimizations

vinodganesan/DAA

Practice codes for DAA course

vinodganesan/git-flight-rules

Flight rules for git

vinodganesan/GSM

Gate-Shift Networks for Video Action Recognition

vinodganesan/hardware-aware-transformers

[ACL 2020] HAT: Hardware-Aware Transformers for Efficient Natural Language Processing

vinodganesan/imagenet18

Train ImageNet in 18 minutes on AWS

vinodganesan/LeetCode-1

:pencil: Python / C++ 11 Solutions of All 468 LeetCode Questions

vinodganesan/nasbench_tf2.0

vinodganesan/Neural-Networks-on-Silicon

This is a collection of works on neural networks and neural accelerators.

vinodganesan/neuro-vectorizer

NeuroVectorizer is a framework that uses deep reinforcement learning (RL) to predict optimal vectorization compiler pragmas for for loops in C and C++ codes.

vinodganesan/once-for-all-1

[ICLR 2020] Once for All: Train One Network and Specialize it for Efficient Deployment

vinodganesan/proxylessnas

[ICLR 2019] ProxylessNAS: Direct Neural Architecture Search on Target Task and Hardware

vinodganesan/riscv-tests

vinodganesan/shaktiFPU

This repository contains the codebase of Floating Point Unit used in different variants of the SHAKTI Processor effort

vinodganesan/shaktiSim

This archived codebase is a simple RISC-V Instruction Set Simulator designed to verify SHAKTI cores

vinodganesan/simpleSLIDE

vinodganesan/spatial-tuts

vinodganesan/temporal-shift-module

[ICCV 2019] TSM: Temporal Shift Module for Efficient Video Understanding

vinodganesan/TRN-pytorch

Temporal Relation Networks

vinodganesan/Vector-Accelerator

This is an archived repository of an older version of Vector Processor (based on Berkeley's Hwacha) designed at SHAKTI group IIT Madras

vinodganesan/vinodganesan.github.io