visionvlsi
“Vision-VLSI Industry Training Institute” is committed to provide hands-on online training on open-source EDA Tools along with subjects required for IC design.
Vision-VLSI Industry Training InstituteHyderabad
Pinned Repositories
visionvlsi's Repositories
visionvlsi/msvsd_one_bit_adc
VSD Research Program
visionvlsi/OpenROAD-flow-scripts
OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
visionvlsi/OpenROAD
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
visionvlsi/modelsim_prac
visionvlsi/ngspice_tutorials
visionvlsi/verification_using_cocotb_2022_batch
visionvlsi/fft_2022_batch
visionvlsi/caravel_gf180_koggestone_adder_project
visionvlsi/git_test_add
visionvlsi/SystemVerilog_Course
This is a detailed SystemVerilog course
visionvlsi/myhdl_tutorial_2022_batch
visionvlsi/dft_tessent
visionvlsi/uart_2022_batch
visionvlsi/adders_2022_batch
visionvlsi/Universal_Verification_Methodology
visionvlsi/verilog2vhdl
visionvlsi/openlane_with_gf180_sky130
visionvlsi/wget
visionvlsi/test_1
visionvlsi/vim_tutorial
visionvlsi/dpll
A simple SystemVerilog digital phase-locked loop based (roughly) on TI's SDLA005B application note. The design includes a SystemVerilog testbench demonstrating a full generator, driver, monitor, and scoreboard testbench environment.
visionvlsi/VerilogProjects
All projects that utilize the Verilog & SystemVerilog HDL's.
visionvlsi/Verification_Training
visionvlsi/qflowinstallation
visionvlsi/100DaysOfRTL
100 Days of RTL
visionvlsi/vlsi_sites
visionvlsi/challenges-zakirhussainsve-python-based-verification
challenges-zakirhussainsve created by GitHub Classroom
visionvlsi/mini_projects
visionvlsi/sha
visionvlsi/cadence_genus