New daily trending repos in Verilog
vitalets opened this issue · 28 comments
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New daily trending repos in Verilog!
pConst / basic_verilog
Must-have verilog systemverilog modules
+2 stars today
Practical-UVM-Step-By-Step / Practical-UVM-IEEE-Edition
This is the repository for the IEEE version of the book
Obijuan / open-fpga-verilog-tutorial
Learn how to design digital systems and synthesize them into an FPGA using only opensource tools
New daily trending repos in Verilog!
ekknod / pcileech-wifi
pcileech-fpga with wireless card emulation
IObundle / iob-soc
RISC-V System on Chip Template
New daily trending repos in Verilog!
secworks / aes
Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.
New daily trending repos in Verilog!
siliconcompiler / lambdalib
Hardware abstraction library
+1 stars today
New daily trending repos in Verilog!
The-OpenROAD-Project / OpenROAD-flow-scripts
OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
+2 stars today
jotego / jtcores
FPGA cores compatible with multiple arcade game machines and KiCAD schematics of arcade games. Working on MiSTer FPGA/Analogue Pocket
nvdla / hw
RTL, Cmodel, and testbench for NVDLA
New daily trending repos in Verilog!
olofk / serv
SERV - The SErial RISC-V CPU
+1 stars today
New daily trending repos in Verilog!
ultraembedded / riscv
RISC-V CPU Core (RV32IM)
New daily trending repos in Verilog!
rejunity / z80-open-silicon
Z80 open-source silicon. Goal is to become a silicon proven, pin compatible, open-source replacement for classic Z80.
+2 stars today
darklife / darkriscv
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
+2 stars today
os-fpga / Raptor
Raptor end-to-end FPGA Compiler and GUI
lnis-uofu / OpenFPGA
An Open-source FPGA IP Generator
New daily trending repos in Verilog!
TinyTapeout / tinytapeout-07
Tiny Tapeout 7
TinyTapeout / tinytapeout-06
Tiny Tapeout 06
New daily trending repos in Verilog!
VerticalResearchGroup / miaow
An open source GPU based off of the AMD Southern Islands ISA.
+3 stars today
New daily trending repos in Verilog!
RESMIRNAIR / 4BIT_RIPPLECOUNTER
efabless / caravel_user_project
https://caravel-user-project.readthedocs.io
New daily trending repos in Verilog!
The-OpenROAD-Project / OpenROAD
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
+1 stars today
New daily trending repos in Verilog!
os-fpga / Raptor_Tools
+1 stars today
ufrisk / pcileech-fpga
FPGA modules used together with the PCILeech Direct Memory Access (DMA) Attack Software
New daily trending repos in Verilog!
learn-cocotb / tutorial
Complete tutorial code.
+1 stars today
New daily trending repos in Verilog!
AngeloJacobo / UberDDR3
Open-sourced DDR3 controller
zeroasiccorp / umi
Universal Memory Interface (UMI)
New daily trending repos in Verilog!
corundum / corundum
Open source FPGA-based NIC and platform for in-network compute
New daily trending repos in Verilog!
riscv-mcu / e203_hbirdv2
The Ultra-Low Power RISC-V Core
+1 stars today
New daily trending repos in Verilog!
Modos-Labs / Caster
Open-source electrophoretics display controller. Mirror of https://gitlab.com/zephray/caster
+1 stars today
New daily trending repos in Verilog!
SI-RISCV / e200_opensource
Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2
New daily trending repos in Verilog!
IObundle / iob-picorv32
IOb_SoC version of the Picorv32 RISC-V Verilog IP core
IObundle / iob-cache
Verilog Configurable Cache
New daily trending repos in Verilog!
YosysHQ / picorv32
PicoRV32 - A Size-Optimized RISC-V CPU
+2 stars today
ekknod / pcileech-multimedia
spartan6 blackmagic
+2 stars today
odriverobotics / ODriveHardware
High performance motor control
New daily trending repos in Verilog!
alexforencich / verilog-ethernet
Verilog Ethernet components for FPGA implementation
+1 stars today
simbricks / simbricks
Main Repository for the SimBricks Modular Full-System Simulation Framework.
+1 stars today
chili-chips-ba / openCologne
Spicing up the first and only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples.
+1 stars today
New daily trending repos in Verilog!
alexforencich / verilog-axi
Verilog AXI components for FPGA implementation
+2 stars today
YosysHQ / yosys-oldtests
Various larger test cases for yosys
os-fpga / yosys_verific_rs
Yosys + (Optional) Verific Integration
New daily trending repos in Verilog!
New daily trending repos in Verilog!
alexforencich / verilog-pcie
Verilog PCI express components
+1 stars today
EttusResearch / uhd
The USRP™ Hardware Driver Repository
New daily trending repos in Verilog!
analogdevicesinc / hdl
HDL libraries and projects
linuxbest / lzs
an open source lzs hardware & software
kitlaan / mojo-empty
Empty makefile project for Mojo development
New daily trending repos in Verilog!
aolofsson / oh
Verilog library for ASIC and FPGA designers
+3 stars today
phoeniX-Digital-Design / phoeniX
phoeniX RISC-V Processor
+1 stars today