vnay01
Hello there! Welcome to my profile! ASIC Designer-in-the-making here, which means the design may have bugs!
Lund, Sweden
Pinned Repositories
algorithmic-trading-python
The repository for freeCodeCamp's YouTube course, Algorithmic Trading in Python
CNN_for_SLR
A trained Convolutional Neural Network implemented on ZedBoard Zynq-7000 FPGA.
Digital-Signal-Processing-Education-Kit
Digital Signal Processing Education Kit
goossens-book-ip-projects
this repository contains all the ip projects presented in the HLS/RISC-V/Computer Architecture book written by Goossens and published by Springer
hw2vec
Machine-Learning-for-Algorithmic-Trading-Second-Edition
Code and resources for Machine Learning for Algorithmic Trading, 2nd edition.
MSOC1_code_repo
Code for assignments - EITF 35
NeuralNetworks
VerilogCodes
A repository of verilog codes of various digital circuits.
vnay01's Repositories
vnay01/Machine-Learning-for-Algorithmic-Trading-Second-Edition
Code and resources for Machine Learning for Algorithmic Trading, 2nd edition.
vnay01/MSOC1_code_repo
Code for assignments - EITF 35
vnay01/NeuralNetworks
vnay01/VerilogCodes
A repository of verilog codes of various digital circuits.
vnay01/algorithmic-trading-python
The repository for freeCodeCamp's YouTube course, Algorithmic Trading in Python
vnay01/CNN_for_SLR
A trained Convolutional Neural Network implemented on ZedBoard Zynq-7000 FPGA.
vnay01/Digital-Signal-Processing-Education-Kit
Digital Signal Processing Education Kit
vnay01/goossens-book-ip-projects
this repository contains all the ip projects presented in the HLS/RISC-V/Computer Architecture book written by Goossens and published by Springer
vnay01/hw2vec
vnay01/Masimulator
Visual RISC-V Simulator
vnay01/MIPS-Processor
5-stage pipelined 32-bit MIPS microprocessor in Verilog
vnay01/Numerical-Recipies-in-C
Native implementation of 'Numerical Recipes in C'
vnay01/nvdl
RTL, Cmodel, and testbench for NVDLA
vnay01/pulpissimo
This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.
vnay01/PythonCode
vnay01/Pyverilog
Python-based Hardware Design Processing Toolkit for Verilog HDL
vnay01/uvmprimer
Contains the code examples from The UVM Primer Book sorted by chapters.
vnay01/vnay01