Pinned Repositories
abc
ABC: System for Sequential Logic Synthesis and Formal Verification
AllwenWeill
benchmarks
EPFL logic synthesis benchmarks
BumpAllocator
模仿Slang的BumpAllocator，基本上都是抄的
GtHomework
Learn-LLVM-13
Learn LLVM 12, published by Packt
MyMemTools
My memory leak checking tool
shua
verilog
wangjunbo4's Repositories
wangjunbo4/verilog
wangjunbo4/BumpAllocator
模仿Slang的BumpAllocator，基本上都是抄的
wangjunbo4/Learn-LLVM-13
Learn LLVM 12, published by Packt
wangjunbo4/MyMemTools
My memory leak checking tool
wangjunbo4/abc
ABC: System for Sequential Logic Synthesis and Formal Verification
wangjunbo4/AllwenWeill
wangjunbo4/benchmarks
EPFL logic synthesis benchmarks
wangjunbo4/chinese-programmer-wrong-pronunciation
**程序员容易发音错误的单词
wangjunbo4/commandlist
VSCode Command Extension
wangjunbo4/Cpp-Templates-2ed
C++11/14/17/20 templates and generic programming, the most complex and difficult technical details of C++, indispensable in building infrastructure libraries.
wangjunbo4/Design-Patterns-in-Cpp17
C++17 implementation of 23 GoF design patterns for zero memory leaks using smart pointers.
wangjunbo4/effective-debugging-zh
effective debugging 中文翻译
wangjunbo4/EffectiveModernCppChinese
《Effective Modern C++》翻译 - 已完成
wangjunbo4/empty
wangjunbo4/helang
何语言，次世代赛博编程语言。
wangjunbo4/highway
Performance-portable, length-agnostic SIMD with runtime dispatch
wangjunbo4/HowToCook
程序员在家做饭方法指南。Programmer's guide about how to cook at home (Chinese).
wangjunbo4/interactive_latencies
Jeff Dean's latency numbers plotted over time
wangjunbo4/modern-cpp-tutorial
📚 Modern C++ Tutorial: C++11/14/17/20 On the Fly | https://changkun.de/modern-cpp/
wangjunbo4/netlist-paths
A library and command-line tool for querying a Verilog netlist.
wangjunbo4/qc-hash
Extremely fast unordered map and set library for C++20
wangjunbo4/recipes
Some code snippets for sharing
wangjunbo4/sv-JTracing
wangjunbo4/sv-tests
Test suite designed to check compliance with the SystemVerilog standard.
wangjunbo4/svls
SystemVerilog language server
wangjunbo4/system-design-primer
Learn how to design large-scale systems. Prep for the system design interview. Includes Anki flashcards.
wangjunbo4/SystemVerilogReference
training labs and examples
wangjunbo4/UHDM
Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
wangjunbo4/wangjunbo4
wangjunbo4/yosys
Yosys Open SYnthesis Suite