wannesm/DAG_Processor

A DAG processor and compiler for a tree-based spatial datapath.

Energy-efficient execution of irregular directed acyclic graphs

The paper proposes a customized parallel architecture for energy-efficient execution of irregular directed acyclic graphs (DAG) from probabilistic machine learning and sparse linear algebra. A targeted compiler is developed to generate a binary program for the custom processor given an arbitrary DAG.

Aim of the experiments

The processor performance reported in the paper are reproduced through SystemVerilog RTL simulation. The processor instructions for the target workloads are generated with the custom compiler, validating the compilation algorithm.

This codebase includes the following components:

1. SystemVerilog-based microarchitectural RTL model of the processor (in ./hw/rtl/) and a testbench (in ./hw/tb/).
2. A Python-based compiler (in ./src/).
3. Input DAGs to reproduce the experiments (in ./data/)

Dependencies

• Anaconda3: For Linux installation, see https://docs.anaconda.com/anaconda/install/linux/#installation
• Synopsys VCS simulator: Used for SystemVerilog simulation.

Installation

Run the following commands to clone this repository and setup python dependencies. This script assumes that Anaconda is already installed.

git clone git@github.com:nimish15shah/DAG_Processor.git
cd DAG_Processor
./install.sh

The installation script creates a conda enviornment and installs the required python dependencies.

Runnning experiments

./run.sh

The script performs the following steps:

• The python-based compiler takes the DAG benchmarks as input and generates binary programs for each benchmark.
• The SystemVerilog testbench reads the binary programs and the data input files generated by the compiler, and executes the RTL simulation (with the proprietary Synopsys VCS simulator) and generates the latency log.
• Finally the charts are plotted according to the data collected during the compilation and RTL simulations.

Disk space requirement: Less than 200MB (not including Anaconda and Synopsys VCS installation).

Experiments runtime: 6-8 hours.

Outputs

The output charts are available at ./out/plots.

• The results of fig. 14 of the paper is reproduced in the ./out/plots/instruction_breakdown.pdf file.
• The results of our processor in fig. 15(a) of the paper is reproduced in the ./out/plots/throughput.pdf file. Throughputs of the rest of the platforms are not reproduced in this codebase and are plotted from a fixed table.

Note: The large DAGs ("Large PC") from table 1 in the paper are not evaluated in this version of the codebase due to large experimental runtime (>24hours).