weedmank

HW Verilog/SV/FPGA/SVA/ABV Design and CDC/RDC/Formal Property Verification Engineer

Canby, OR USA

Pinned Repositories

GPCore
This is the base repo for our graduation project in AlexU 21
Language:SystemVerilog00
RisKy1
Repository for the RisKy1 RISC-V ISA based CPU and various "flavors" of RV32imcZicsr. This design has many parameters/extensions that may be changed in order to tailor the CPU to a specific configuration.
Language:SystemVerilog2 2 122

weedmank's Repositories

weedmank/RisKy1
Repository for the RisKy1 RISC-V ISA based CPU and various "flavors" of RV32imcZicsr. This design has many parameters/extensions that may be changed in order to tailor the CPU to a specific configuration.
Language:SystemVerilog2 2 122
weedmank/GPCore
This is the base repo for our graduation project in AlexU 21
Language:SystemVerilog00