Pinned Repositories
AccDNN
A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.
Accelerating-CNN-with-FPGA
This project accelerates CNN computation with the help of FPGA, for more than 50x speed-up compared with CPU.
CNN_C_forword
使用c语言完成Lenet-5的前向传播过程
convolution_network_on_FPGA
CNN acceleration on virtex-7 FPGA with verilog HDL
DeepLearningC
Simple program to learn CNN (LeNet-5) in pure C
docs
TensorFlow documentation
FlexCNN
MindStudio
SkrSkr
ultra_net
FPGA-based neural network inference project for 2020 DAC System Design Contest
wei8171023's Repositories
wei8171023/CNN_C_forword
使用c语言完成Lenet-5的前向传播过程
wei8171023/MindStudio
wei8171023/SkrSkr
wei8171023/ultra_net
FPGA-based neural network inference project for 2020 DAC System Design Contest
wei8171023/AccDNN
A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.
wei8171023/Accelerating-CNN-with-FPGA
This project accelerates CNN computation with the help of FPGA, for more than 50x speed-up compared with CPU.
wei8171023/docs
TensorFlow documentation
wei8171023/FlexCNN
wei8171023/FPGA
数字IC相关资料
wei8171023/FPGABasedHighPerformanceTargetChecking
it is a set for all the respository of the project.
wei8171023/git_learn
wei8171023/JPG-PNG-to-MNIST-NN-Format
Python/Bash scripts for creating custom Neural Net Training Data -- this repo is for the MNIST format
wei8171023/Learning-DIY-RTOS
自己动手从0到1写嵌入式操作系统 课程的相关资料下载
wei8171023/Learning-NVDLA-Notes
NVDLA is an Open source DL/ML accelerator, which is very suitable for individuals or college students. This is the NOTES when I learn and try. Hope THIS PAGE may Helps you a bit. Contact Me:junning.wu@ia.ac.cn
wei8171023/LightFaceNet
This tensorflow project is based on MobileFaceNet, which use SqueezeNet and ShuffleNet as stem CNN to improve speed.
wei8171023/MaixPy_scripts
micropython scripts for MaixPy
wei8171023/nvdla_compiler
wei8171023/opencv
Open Source Computer Vision Library
wei8171023/protobuf
Protocol Buffers - Google's data interchange format
wei8171023/scalehls
A scalable High-Level Synthesis framework on MLIR
wei8171023/soDLA
Chisel implementation of the NVIDIA Deep Learning Accelerator (NVDLA), with self-driving accelerated
wei8171023/Tengine
Tengine is a lite, high performance, modular inference engine for embedded device
wei8171023/Tensorflow-FaceRecognition
基于MTCNN和MobileFaceNet实现的人脸识别，提供三种预测方式，满足各种需求 。
wei8171023/TIM-VX
Verisilicon Tensor Interface Module
wei8171023/Ultra-Light-Fast-Generic-Face-Detector-1MB
💎1MB lightweight face detection model (1MB轻量级人脸检测模型)
wei8171023/web-model-converter
wei8171023/XJTU-Tripler
This repository is the backup of XJTU-Tripler project, participating dac19 system design contest
wei8171023/Yolo-Fastest
:zap: Yolo universal target detection model combined with EfficientNet-lite, the calculation amount is only 230Mflops(0.23Bflops), and the model size is 1.3MB
wei8171023/yolov2_xilinx_fpga
A demo for accelerating YOLOv2 in xilinx's fpga pynq/zedboard
wei8171023/ZYNQ-NVDLA
NVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.