wengwm18

Student of @beijing Tsinghua University; Student of @edinburgh University and @glasgow University

@Beijing Tsinghua UniversityChina

Pinned Repositories

Assignment-1
Digital Signal Processing: Fourier Transform
Language:Python10
Assignment-2
Digital Signal processing: FIR filters
Language:Python00
Assignment-3
Digital Signal processing: IIR filters
Language:Python00
Logic-design-FPGA-ISE
**Tsinghua University Logic Design using ISE**
Language:Verilog0 2 00

wengwm18's Repositories

wengwm18/Assignment-1
Digital Signal Processing: Fourier Transform
Language:Python10
wengwm18/Assignment-2
Digital Signal processing: FIR filters
Language:Python00
wengwm18/Assignment-3
Digital Signal processing: IIR filters
Language:Python00
wengwm18/Logic-design-FPGA-ISE
**Tsinghua University Logic Design using ISE**
Language:Verilog0 2 00