Pinned Repositories
cocotb
cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
core-v-verif
Functional verification project for the CORE-V family of RISC-V cores.
d2l-zh
《动手学深度学习》：面向中文读者、能运行、可讨论。中英文版被60多个国家的400多所大学用于教学。
default-settings
Default settings for elementary OS
ksim
model-optimization
A suite of tools that users, both novice and advanced, can use to optimize machine learning models for deployment and execution.
MOSS
An open-source tool-augmented conversational language model from Fudan University
pyuvm
The UVM written in Python
riscv
RISC-V CPU Core (RV32IM)
riscv_verilator_model
RISCV model for Verilator/FPGA targets
wenson-wu's Repositories
wenson-wu/cocotb
cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
wenson-wu/core-v-verif
Functional verification project for the CORE-V family of RISC-V cores.
wenson-wu/d2l-zh
《动手学深度学习》：面向中文读者、能运行、可讨论。中英文版被60多个国家的400多所大学用于教学。
wenson-wu/default-settings
Default settings for elementary OS
wenson-wu/ksim
wenson-wu/model-optimization
A suite of tools that users, both novice and advanced, can use to optimize machine learning models for deployment and execution.
wenson-wu/MOSS
An open-source tool-augmented conversational language model from Fudan University
wenson-wu/pyuvm
The UVM written in Python
wenson-wu/riscv
RISC-V CPU Core (RV32IM)
wenson-wu/riscv_verilator_model
RISCV model for Verilator/FPGA targets
wenson-wu/tensorflow
An Open Source Machine Learning Framework for Everyone
wenson-wu/uvm-python
UVM 1.2 port to Python
wenson-wu/verilator
Verilator open-source SystemVerilog simulator and lint system
wenson-wu/vortex