wenxuan-hu

Pinned Repositories

book
Computer Networks: A Systems Approach -- Textbook
Language:Python00
child_safety
project for UW EE542
11
Cores-SweRV-EH2
Language:SystemVerilog00
CS-Notes
:books: 技术面试必备基础知识、Leetcode、计算机操作系统、计算机网络、系统设计
00
cse414
cse414
00
CSE451
CSE 451: Introduction to Operating Systems (taught by Ed Lazowska)
Language:Shell00
cse550
CSE550: Systems for All
Language:Python00
cse550-a1
Language:C00
CSE5500
Language:C00
SSRL_work
work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework
Language:SystemVerilog276

wenxuan-hu's Repositories

wenxuan-hu/SSRL_work
work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework
Language:SystemVerilog276
wenxuan-hu/child_safety
project for UW EE542
11
wenxuan-hu/book
Computer Networks: A Systems Approach -- Textbook
Language:Python00
wenxuan-hu/Cores-SweRV-EH2
Language:SystemVerilog00
wenxuan-hu/CS-Notes
:books: 技术面试必备基础知识、Leetcode、计算机操作系统、计算机网络、系统设计
00
wenxuan-hu/cse414
cse414
00
wenxuan-hu/CSE451
CSE 451: Introduction to Operating Systems (taught by Ed Lazowska)
Language:Shell00
wenxuan-hu/cse550
CSE550: Systems for All
Language:Python00
wenxuan-hu/cse550-a1
Language:C00
wenxuan-hu/CSE5500
Language:C00
wenxuan-hu/cse5501
Repo for CSE550
wenxuan-hu/DDR4MemoryController
HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.
wenxuan-hu/digital_video_introduction
A hands-on introduction to video technology: image, video, codec (av1, vp9, h265) and more (ffmpeg encoding).
wenxuan-hu/e200_opensource
Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2
wenxuan-hu/EE562
EE 562 (Autumn 2020): Artificial Intelligence for Engineers
wenxuan-hu/eh2_core
EH2: RSIC-V processor from Western Digital
wenxuan-hu/fullstack-tutorial
🚀 fullstack tutorial 2022，后台技术栈/架构师之路/全栈开发社区，春招/秋招/校招/面试
wenxuan-hu/ibex
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
wenxuan-hu/ISP_ASIC
RTL for ISP
Language:Verilog
wenxuan-hu/litedram
Small footprint and configurable DRAM core
wenxuan-hu/LM-RISCV-DV
An Open-Source Design and Verification Environment for RISC-V
wenxuan-hu/NeurIPS2023-One-Fits-All
The official code for "One Fits All: Power General Time Series Analysis by Pretrained LM (NeurIPS 2023 Spotlight)"
wenxuan-hu/risc-v_cpu
This is digital IC design project for UW EE525
wenxuan-hu/riscv-boom
SonicBOOM: The Berkeley Out-of-Order Machine
wenxuan-hu/riscv-dv
Random instruction generator for RISC-V processor verification
wenxuan-hu/rvv-intrinsic-doc
wenxuan-hu/Summer2023-Internships
Collection of Summer 2023 tech internships!
wenxuan-hu/verilator
Verilator open-source SystemVerilog simulator and lint system