Pinned Repositories
2016_NXP_ChenFeng
2016年恩智浦杯全国大学生智能汽车大赛，武汉理工大学，电轨竞速组，电轨节能组
iRhythm
2018 Synopsys ARC®杯电子设计竞赛项目——iRhythm
LED256
大一参加学院流水灯大赛的两个作品，分别获得1、2名
MK64F-platform
A PCB platform based on the architecture of Arm + FPGA
PRM-RA-ACC
real repo of accelerator
PRM_Robotic_Arm
硕士研究生毕业设计总仓
Rift2Core
Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.
RiftCore
RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System
verilogRisc
基于蜂鸟E203的魔改
YJ432-PL-PS
ARM+FPGA borad demo
whutddk's Repositories
whutddk/RiftCore
RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System
whutddk/Rift2Core
Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.
whutddk/whutddk.github.io
whutddk/BitcoinWhitePaper
whutddk/caravel-gf180mcu
This repository is the GF180MCU port of Caravel. For more information about Caravel, see the original repo at https://github.com/efabless/caravel.
whutddk/caravel_user_project
https://caravel-user-project.readthedocs.io
whutddk/chisel3
Chisel 3: A Modern Hardware Design Language
whutddk/constellation
A Chisel RTL generator for network-on-chip interconnects
whutddk/cva6
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
whutddk/DARC
Decentralized Autonomous Regulated Company (DARC), a company virtual machine that runs on any EVM-compatible blockchain, with on-chain law system, multi-level tokens and dividends mechanism.
whutddk/evil.js
Use with caution
whutddk/jtdx
JTDX
whutddk/mpwData
This is a repo storing the files in each MPW
whutddk/OSSRH-81803
whutddk/Rift2Fake_gf180_mpw0
whutddk/Rift2Fake_sky130_resubmission
whutddk/Rift2Go_2300_GF180_MPW0
whutddk/Rift2Go_2300_GF180_MPW1
whutddk/Rift2Go_2300_Sky130_MPW8
whutddk/Rift2Go_2310_Sky130_MPW7
whutddk/Rift2Go_2320_Sky130_MPW8
whutddk/Rift2Go_2330_Sky130_MPW8
whutddk/riscv-cores-list
RISC-V Cores, SoC platforms and SoCs
whutddk/riscv-isa-manual
RISC-V Instruction Set Manual
whutddk/riscv-online-asm
RISC-V Online Assembler using Emscripten, Gnu Binutils
whutddk/riscv-p-spec
RISC-V Packed SIMD Extension
whutddk/riscv-test-env
whutddk/riscv-torture
RISC-V Torture Test
whutddk/sifive-blocks
Common RTL blocks used in SiFive's projects
whutddk/ysyx-workbench