Pinned Repositories
amaranth
A modern hardware definition language and toolchain based on Python
bin-tree-diff
A recursive diff for toolchain refactoring equivalence testing all the way down to object files in static libraries
csv-sampler
riscv-benchmark-automation
Collection of benchmarks to run for the RISC-V architecture on Spike, with a TUI made with curses.
widlarizer's Repositories
widlarizer/riscv-benchmark-automation
Collection of benchmarks to run for the RISC-V architecture on Spike, with a TUI made with curses.
widlarizer/amaranth
A modern hardware definition language and toolchain based on Python
widlarizer/bin-tree-diff
A recursive diff for toolchain refactoring equivalence testing all the way down to object files in static libraries
widlarizer/csv-sampler
widlarizer/embench-iot
The main Embench repository
widlarizer/esp-idf
Espressif IoT Development Framework. Official development framework for Espressif SoCs.
widlarizer/esphome-devices
esphome configs for my sensors
widlarizer/lang-talk-unbash
Slides for my talk about coping with a bashy world
widlarizer/llvm-project
The LLVM Project is a collection of modular and reusable compiler and toolchain technologies.
widlarizer/matklad.github.io
My coding related blog
widlarizer/meetups
A community around PL at Prague.
widlarizer/microzig
Unified abstraction layer and HAL for several microcontrollers
widlarizer/nixpkgs
Nix Packages collection & NixOS
widlarizer/OpenLane
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
widlarizer/OpenROAD
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
widlarizer/OpenROAD-flow-scripts
OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
widlarizer/pandoc-minted
A pandoc filter that has the LaTeX writer use minted for typesetting code.
widlarizer/prettyplace
The cutest standard cell placer yet
widlarizer/qtrvsim
RISC-V CPU simulator for education purposes
widlarizer/regz
Generate zig code from ATDF or SVD files for microcontrollers.
widlarizer/riscv-tests
widlarizer/sycl-badge
MicroZig running on the PyBadge! https://badgesim.microzig.tech/
widlarizer/tt-support-tools
tools used by project repos to test configuration, generate OpenLane run summaries and documentation
widlarizer/tt02-chase-the-beat
Chase the beat - open source silicon for TinyTapeout 2
widlarizer/vexbench
VexRISCV for compiler benchmarking
widlarizer/VexRiscv
A FPGA friendly 32 bit RISC-V CPU implementation
widlarizer/vga-thingy
Submission template for Tiny Tapeout 7 - Verilog HDL Projects
widlarizer/winamp
Iconic media player
widlarizer/yosys
Yosys Open SYnthesis Suite
widlarizer/zig
General-purpose programming language and toolchain for maintaining robust, optimal, and reusable software.