/ECE485

Stuff for ECE485

Primary LanguagePython

Stuff for HW4 project

Table of contents

cacheFSM.py -- super simple FSM and testbench for it, written in python using the MyHDL package

cacheFSM.v -- MyHDL generated verilog code, based on cacheFSM3.py

tb_cacheFSM.v -- MyHDL generated verilog code, based on cacheFSM3.py

testbench.vcd -- VCD file that shows signal traces, can be viewed with GTKWave

timing.pdf -- print out of testbench.vcd

Team members

William Harrington

Ahmed Abdulkareem