This is a HyperBus leader for accessing external HyperRAM devices from an FPGA. Developed and tested up to 100MHz on an Intel Cyclone 10 LP Evaluation board with onboard 16MB HyperRAM chip and VexRiscv RISC-V CPU.
A clock crossing FIFO and Wishbone interface are provided. The core is implemented in Verilog and is easily integrated into FuseSoC designs by the provided CAPI2 core file.
The RAM clock and wishbone clock are independent and each side is driven by its own clock with synronization using a dual clock async FIFO. Requests from the wishbone bus are queued into a command and data FIFO, and the HyberBus core will queue response data and acks back to the wishbone side.
- Test 166MHz
- Add stream support to the FIFO interface for DMA
- Add support for Wishbone burst transfers
- Integrate an internal cache to reduce HyperBus command/address bytes and latency overhead
- Fix SDC constraints
- Add additional bus interfaces
- Currently only Intel FPGAs are supported
- Intel
ALTDDIO_BIDIRis used internally for DDR IO on theDQandRWDSsignals - Other DDR primitives may be added for additional target FPGAs
- Intel
- A 100MHz clock, as well as a 90 degree phase shifted clock (2500ps shift) must be provided by a PLL
- Call SDC function included in
data/hyperbus.sdcfor assigning clock and data pin constrains
- Tested on an Intel Cyclone 10 LP Evaluation Kit board
- Includes onboard 128Mbit HyperRAM chip