Pinned Repositories
320-Two-Phase-Handshake
Demonstration on the Two Phase Handshake in Verilog
apb2ic
APB to I2C converter Design & TB
apb_spi_master
Asynchronous-FIFO
Asynchronous fifo in verilog
buggy_soc1
Buggy Pulpino SOC
clock_reset
forge
Perl_OOP
Perl Package for better programming
System-Bus-Design-Verilog
This is a Multi master Multi slave compatible system bus design modeled using verilog. This is much like AMBA AHB Specification
verilog_everyday
the result of verilog everyday activity
wwei1988's Repositories
wwei1988/buggy_soc1
Buggy Pulpino SOC
wwei1988/320-Two-Phase-Handshake
Demonstration on the Two Phase Handshake in Verilog
wwei1988/apb2ic
APB to I2C converter Design & TB
wwei1988/apb_spi_master
wwei1988/Asynchronous-FIFO
Asynchronous fifo in verilog
wwei1988/clock_reset
wwei1988/forge
wwei1988/Perl_OOP
Perl Package for better programming
wwei1988/System-Bus-Design-Verilog
This is a Multi master Multi slave compatible system bus design modeled using verilog. This is much like AMBA AHB Specification
wwei1988/verilog_everyday
the result of verilog everyday activity