wyvernSemi
Semi-retired logic, s/w and systems designer, with a background in high performance computing and wireless/cellular, developing open-source IP for all to use
Cambridge, United Kingdom
Pinned Repositories
cpu6502
A 6502 Instruction Set Simulator
cpu8051
Intel(R) 8051 Instruction Set Simulator
eccExamples
Error correction and detection example Verilog (hamming and Reed-Solomon) to accompany presentation material
mem_model
High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model
pcievhost
PCIe (1.0a to 2.0) Virtual host model for verilog
riscV
Open source ISS and logic RISC-V 32 bit project
tcpIpPg
10GbE XGMII TCP/IPv4 packet generator for Verilog
usbModel
USB virtual model in C++ for Verilog
vproc
Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments
winfilter
WinFilter graphical FIR filter design program
wyvernSemi's Repositories
wyvernSemi/jfif
JFIF and JPEG file decoder software
wyvernSemi/slzw
Simple LZW codec in C
wyvernSemi/lm32fpga
FPGA development board (DE1) targetted lm32 based systems design for Verilog