Mixed usage of "downto" and "to" in indexing in AGWB VHDL code

[wzab]

Current code of AGWB tends to use downto when indexing bit vectors and to for arrays.

In the code that we are using it is handled in different way. In GBT-FPGA they often use the "old" convention.
In general-cores there are different cases. Just take a look at:

https://ohwr.org/project/general-cores/blob/96630ec6636b3ea17b240b6c398a1cdf6c761028/modules/wishbone/wb_crossbar/xwb_crossbar.vhd#L65

and

https://ohwr.org/project/general-cores/blob/96630ec6636b3ea17b240b6c398a1cdf6c761028/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd#L22

(Both are from the same version!)

Now @m-kru suggests, that we shoud clean it up. So we are switching to using downto, wherever possible,

[wzab]

OK. The indexing order is fixed. The "downto" is used wherever possible (even a few arrays of integers are indexed with "downto", which resulted in necessity to reverse tuples:

agwb/src/wb_block.py

Line 496 in a1cdf1c

str(GLB.variants - 1) + " downto 0 ) := " + str(tuple(self.variants[::-1])) + ";\n"

agwb/src/wb_block.py

Line 1519 in a1cdf1c

str(GLB.variants - 1) + " downto 0 ) := " + str(tuple(a_r.variants[::-1])) + ";\n"

or to reorganize loops:

agwb/src/wb_block.py

Line 1487 in a1cdf1c

for i in range(GLB.variants-1,-1,-1): # Reverse order due to "downto"

)

Anyway, it seems that now the code generation works correctly.
I close the issue.