Issues
- 0
- 4
- 1
Incorrect code generated when the default value is set in the vector of control registers
#64 opened by wzab - 1
Certain problems with RelaxNG syntax validation
#62 opened by wzab - 0
- 9
Better handling of BlackBoxes - support for HLS?
#61 opened by wzab - 3
Mistake in wb_cdc?
#59 opened by wzab - 0
Connecting Wishbone busses - naming conventions
#60 opened by wzab - 3
Python backend support vor variants
#56 opened by wzab - 1
- 1
- 3
Implementation of the "extended interface" - to make use of the extended features of IPbus, E2bus or CBM DCA - how to implement RMW?
#55 opened by wzab - 0
Current CDC block is inefficient for connecting clock domains using synchronous clocks with different frequencies
#54 opened by wzab - 1
Enabling stb generates incompatible port name.
#52 opened by m-kru - 2
- 1
Unify `reps` attribute behavior.
#37 opened by m-kru - 1
- 2
Validation of system description XML with RelaxNG sometimes gives incorrect error reports
#51 opened by wzab - 2
- 0
Better granularity of the version identifiers.
#47 opened by wzab - 4
Problem with the newest version of GHDL
#46 opened by wzab - 1
- 0
Add regression testing.
#44 opened by m-kru - 0
Split code into packages and modules.
#43 opened by m-kru - 0
Treating subblock elements as a block instantiation.
#42 opened by m-kru - 0
Improve format of VHDL constants generation.
#25 opened by m-kru - 0
Superfluous assignment in to_slv() functions converting from custom types to std_logic_vector.
#39 opened by m-kru - 0
Unnecessary general_cores dependency.
#34 opened by m-kru - 0
- 0
- 0
- 1
Revise hdl parameter for FuseSoc wrapper
#35 opened by m-kru - 0
Remove agwb_ prefix from VHDL files and entities.
#31 opened by m-kru - 0
- 0
Document base parameter for agwb.Block class
#33 opened by m-kru - 0
- 3
Bus behavior on internal address over range.
#8 opened by m-kru - 0
Reduce amount of console output.
#26 opened by m-kru - 0
In the HTML documentation the length of object (blocks or register) vectors is not shown
#24 opened by wzab - 1
Scalability of vectors of subblocks
#23 opened by wzab - 0
Improved handling of blackboxes
#22 opened by wzab - 0
- 4
Generation of C headers
#15 opened by wzab - 1
Block without registers
#4 opened by gumaas - 1
Register identification update
#5 opened by gumaas - 2
- 2
- 0
- 0
Option to define active reset value.
#9 opened by m-kru - 1
To add support for "blackboxes"
#1 opened by wzab