Pinned Repositories
Accel_AES
advanced-uvm-hawkins
advanced-uvm-second_edition
Code for the second edition of Advanced UVM.
ahb-tl-bridge
SystemVerilog implementation of the AHB to TileLink UL (Uncached Lightweight) bridge
core-v-verif
Functional verification project for the CORE-V family of RISC-V cores.
cva6
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
opentitan
OpenTitan: Open source silicon root of trust
xiaoweish's Repositories
xiaoweish/ara
The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core
xiaoweish/core-v-verif
Functional verification project for the CORE-V family of RISC-V cores.
xiaoweish/cva6
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
xiaoweish/caliptra-rtl
HW Design Collateral for Caliptra RoT IP
xiaoweish/cocotbext-pcie
PCI express simulation framework for Cocotb
xiaoweish/core-v-cores
CORE-V Family of RISC-V Cores
xiaoweish/cosim-arch-checker
Framework to perform DUT vs ISS (Whisper) lockstep architectural checks
xiaoweish/cshenv
My personal TCSH login scripts and vimrc files.
xiaoweish/Design-Verification
Course content for the University of Bristol Design Verification course.
xiaoweish/fixSegfaultVCS
There is segmentation fault of VCS which should be fixed.
xiaoweish/leon3-grlib-gpl-mirror
Git mirror of Gaisler's GRLIB/Leon3 releases
xiaoweish/newlib-cygwin
xiaoweish/openc906
OpenXuantie - OpenC906 Core
xiaoweish/opene902
OpenXuantie - OpenE902 Core
xiaoweish/opene906
OpenXuantie - OpenE906 Core
xiaoweish/renode
Renode - Antmicro's open source simulation and virtual development framework for complex embedded systems
xiaoweish/riscv-formal-YosysHQ
RISC-V Formal Verification Framework
xiaoweish/riscv-isa-sim
RISC-V Functional ISA Simulator
xiaoweish/riscvISACOV
SystemVerilog Functional Coverage for RISC-V ISA
xiaoweish/rmem
rmem public repo
xiaoweish/rules_verilog
Bazel build rules for compiling Verilog
xiaoweish/svlib
svlib was presented for the first time at DVCon in 2014, providing a programmer's utility library for SystemVerilog. See also http://www.verilab.com/resources/svlib
xiaoweish/tunasync-scripts
Custom scripts for mirror jobs
xiaoweish/ucli-vim-syntax
Synopsys UCLI Vim Syntax (Including Verdi commands)
xiaoweish/uvm-source
Mirror of https://www.accellera.org/downloads/standards/uvm, starting from uvm-1.2.
xiaoweish/verilog_systemverilog.vim
Verilog/SystemVerilog Syntax and Omni-completion
xiaoweish/vim-log-highlighting
Syntax highlighting for generic log files in VIM
xiaoweish/vim-pathogen
pathogen.vim: manage your runtimepath
xiaoweish/vim-sail-higlighting
Copied from : https://github.com/rems-project/sail/tree/sail2/editors/vim
xiaoweish/vortex