Pinned Repositories
Accel_AES
advanced-uvm-hawkins
advanced-uvm-second_edition
Code for the second edition of Advanced UVM.
ahb-tl-bridge
SystemVerilog implementation of the AHB to TileLink UL (Uncached Lightweight) bridge
core-v-verif
Functional verification project for the CORE-V family of RISC-V cores.
cva6
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
opentitan
OpenTitan: Open source silicon root of trust
xiaoweish's Repositories
xiaoweish/core-v-verif
Functional verification project for the CORE-V family of RISC-V cores.
xiaoweish/cva6
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
xiaoweish/opentitan
OpenTitan: Open source silicon root of trust
xiaoweish/baremetal-examples-codasip
xiaoweish/bringup-bench
Bringup-Bench is a collection of standalone minimal library and system dependence benchmarks useful for bringing up newly designed CPUs, accelerators, compilers and operating systems. You probably don't need Bringup-Bench, but if you do, you probably need it badly!
xiaoweish/cheriot-ibex
cheriot-ibex is a RTL implementation of CHERIoT ISA based on LowRISC's Ibex core.
xiaoweish/Cores-SweRV-riscof
SweRV EH1 core
xiaoweish/Hazard3
3-stage RV32IMACZb* processor with debug
xiaoweish/hdl-analogdevicesinc
HDL libraries and projects
xiaoweish/litmus-tests-armv8a-system-vmsa
Virtual memory litmus tests
xiaoweish/microtesk-riscv-ispras
xiaoweish/neorv32
:desktop_computer: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
xiaoweish/nuclei-sdk
Nuclei RISC-V Software Development Kit
xiaoweish/pydrofoil
A fast RISC-V emulator based on the RISC-V Sail model, and an experimental ARM one
xiaoweish/qemu
Official QEMU mirror. Please see https://www.qemu.org/contribute/ for how to submit changes to QEMU. Pull Requests are ignored. Please only use release tarballs from the QEMU website.
xiaoweish/riscv-aia
AIA IP compliant with the RISC-V AIA spec
xiaoweish/riscv-fast-interrupt
Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)
xiaoweish/riscv-isa-sim
RISC-V Functional ISA Simulator
xiaoweish/riscv-perf-model
Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model
xiaoweish/riscv-tests
xiaoweish/riscv.vim
RISC-V Assembly Syntax Highlighting for Vim
xiaoweish/river_core
RiVer Core is an open source Python based RISC-V Core Verification framework.
xiaoweish/rocket-tools
Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)
xiaoweish/sail-riscv
Sail RISC-V model
xiaoweish/scr1
SCR1 is a high-quality open-source RISC-V MCU core in Verilog
xiaoweish/tarmac-trace-utilities
Tools for analyzing and browsing Tarmac instruction traces.
xiaoweish/uvm-components
Contains commonly used UVM components (agents, environments and tests).
xiaoweish/VexRiscv
A FPGA friendly 32 bit RISC-V CPU implementation
xiaoweish/vim-pathogen
pathogen.vim: manage your runtimepath
xiaoweish/vortex