xiaoyuehai

DITES

Fixed_weight_res_stdp

coop with gatech

FPGA-NHAP

FPGA_SNN_STDP

FPGA acceleration of a Spike-Timing-Dependent Plasticity learning algorithm for Spiking Neural Networks

FPGA_Spiking_NN

CORDIC-SNN, followed with "Unsupervised learning of digital recognition using STDP" published in 2015, frontiers

kamikaze

Light-weight RISC-V RV32IMC microcontroller core.

NoC

NoC

RANC

ReckOn

ReckOn: A Spiking RNN Processor Enabling On-Chip Learning over Second-Long Timescales - HDL source code and documentation.

S2NN-HLS

Spiking neural network for Zynq devices with Vivado HLS

xiaoyuehai/DITES

xiaoyuehai/NoC

NoC

xiaoyuehai/S2NN-HLS

Spiking neural network for Zynq devices with Vivado HLS

xiaoyuehai/Fixed_weight_res_stdp

coop with gatech

xiaoyuehai/FPGA-NHAP

xiaoyuehai/FPGA_SNN_STDP

FPGA acceleration of a Spike-Timing-Dependent Plasticity learning algorithm for Spiking Neural Networks

xiaoyuehai/FPGA_Spiking_NN

CORDIC-SNN, followed with "Unsupervised learning of digital recognition using STDP" published in 2015, frontiers

xiaoyuehai/kamikaze

Light-weight RISC-V RV32IMC microcontroller core.

xiaoyuehai/RANC

xiaoyuehai/ReckOn

ReckOn: A Spiking RNN Processor Enabling On-Chip Learning over Second-Long Timescales - HDL source code and documentation.

xiaoyuehai/SpikingNeuralNet

Spiking neural network implementation using Verilog with LIF (Leaky Integrate-and-Fire) neurons

xiaoyuehai/STBP-train-and-compression

STBP is a way to train SNN with datasets by Backward propagation.Using this Repositories allows you to train SNNS with STBP and quantize SNNS with QAT to deploy to neuromorphological chips like Loihi and Tianjic.

xiaoyuehai/StepSTDP

StepSTDP is a new improved STDP algorithm for SNN training, which has good feasibility in hardware implementation

xiaoyuehai/trng

True Random Number Generator core implemented in Verilog.

xiaoyuehai/XCryptCore

Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)