xiekailiang

electron-ssr-backup

electron-ssr原作者删除了这个伟大的项目，故备份了下来，不继续开发,且用且珍惜

idb-keyval

A super-simple-small promise-based keyval store implemented with IndexedDB

mnist_fpga

using xilinx xc6slx45 to implement mnist net

mybar2

pp4fpgas

Parallel Programming for FPGAs -- An open-source high-level synthesis book

Tutorial

u-boot-sunxi

Allwinner A1x native u-boot support

Verilog-Practice

HDLBits website practices & solutions

Vitis_Embedded_Platform_Source

vivado-hls-broadcast-optimization

[DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency

xiekailiang/Vitis_Embedded_Platform_Source

xiekailiang/vivado-hls-broadcast-optimization

[DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency

xiekailiang/electron-ssr-backup

electron-ssr原作者删除了这个伟大的项目，故备份了下来，不继续开发,且用且珍惜

xiekailiang/idb-keyval

A super-simple-small promise-based keyval store implemented with IndexedDB

xiekailiang/mnist_fpga

using xilinx xc6slx45 to implement mnist net

xiekailiang/mybar2

xiekailiang/pp4fpgas

Parallel Programming for FPGAs -- An open-source high-level synthesis book

xiekailiang/Tutorial

xiekailiang/u-boot-sunxi

Allwinner A1x native u-boot support

xiekailiang/Verilog-Practice

HDLBits website practices & solutions

xiekailiang/Vitis-AI

Vitis AI is Xilinx’s development stack for AI inference on Xilinx hardware platforms, including both edge devices and Alveo cards.

xiekailiang/Vitis-Tutorials

xiekailiang/Vitis_Libraries

Vitis Libraries

xiekailiang/Zynq-7000-DPU-TRD

Zynq-7000 DPU TRD