xinhaisc

Pinned Repositories

core_ddr3_controller
A DDR3 memory controller in Verilog for various FPGAs
Language:Verilog00
drawio-desktop
Official electron build of draw.io
Language:Shell00
Ethernet-design-verilog
Gigabit Ethernet UDP communication driver
Language:Verilog00
FastGithub
github加速神器，解决github打不开、用户头像无法加载、releases无法上传下载、git-clone、git-pull、git-push失败等问题
Language:C#00
FPGA_SOBLE_OV7670
FPGA_SOBLE_OV7670
Language:Verilog00
FreeRTOS-Kernel
FreeRTOS kernel files only, submoduled into https://github.com/FreeRTOS/FreeRTOS and various other repos.
Language:C00
lwip
lwip mirror
Language:C00
ML2021-Spring
**Official** 李宏毅 (Hung-yi Lee) 機器學習 Machine Learning 2021 Spring
Language:Jupyter Notebook00
Modbus
一个Modbus通讯协议栈
Language:C00

xinhaisc's Repositories

xinhaisc/FreeRTOS-Kernel
FreeRTOS kernel files only, submoduled into https://github.com/FreeRTOS/FreeRTOS and various other repos.
xinhaisc/drawio-desktop
Official electron build of draw.io
xinhaisc/FastGithub
github加速神器，解决github打不开、用户头像无法加载、releases无法上传下载、git-clone、git-pull、git-push失败等问题
xinhaisc/core_ddr3_controller
A DDR3 memory controller in Verilog for various FPGAs
xinhaisc/ML2021-Spring
**Official** 李宏毅 (Hung-yi Lee) 機器學習 Machine Learning 2021 Spring
xinhaisc/Modbus
一个Modbus通讯协议栈
xinhaisc/Ethernet-design-verilog
Gigabit Ethernet UDP communication driver
xinhaisc/FPGA_SOBLE_OV7670
FPGA_SOBLE_OV7670
Language:Verilog
xinhaisc/lwip
lwip mirror