xiyurain

bert

TensorFlow code and pre-trained models for BERT

dana

Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel

Heterogeneous-Shared-Memory-messaging-layer

Heterogeneous-ShMem-Messaging-Layer

ivshmem-MsgLayer

messaging layer based on ivshmem

Ring-Buffer-on-IVshmem

a ring buffer device driver with PCIe based on QEMU Inter-VM shared memory

UltraMIPS-CPU

A Dual-issue MIPS CPU core feature with 5-level-pipeline, cache, Branch Predictor, TLB, UNIX OS SoC.

UltraMIPS_NSCSCC

UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.

UltraOS

A Rust based Multicore OS developed by UltraTeam, HITsz. Currently updated on https://gitee.com/LoanCold/ultraos_backup

xiyurain.github.io

Github Pages template for academic personal websites, forked from mmistakes/minimal-mistakes

xiyurain/UltraOS

A Rust based Multicore OS developed by UltraTeam, HITsz. Currently updated on https://gitee.com/LoanCold/ultraos_backup

xiyurain/UltraMIPS-CPU

A Dual-issue MIPS CPU core feature with 5-level-pipeline, cache, Branch Predictor, TLB, UNIX OS SoC.

xiyurain/Ring-Buffer-on-IVshmem

a ring buffer device driver with PCIe based on QEMU Inter-VM shared memory

xiyurain/bert

TensorFlow code and pre-trained models for BERT

xiyurain/dana

Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel

xiyurain/Heterogeneous-Shared-Memory-messaging-layer

xiyurain/Heterogeneous-ShMem-Messaging-Layer

xiyurain/ivshmem-MsgLayer

messaging layer based on ivshmem

xiyurain/UltraMIPS_NSCSCC

UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.

xiyurain/xiyurain.github.io

Github Pages template for academic personal websites, forked from mmistakes/minimal-mistakes