xuequanli1021

xuequanli1021's Stars

• rad68/round-robin

  Verilog implementation of a fast and lightweight round-robin arbiter

  Language:Verilog1

• krishnakumarbhat/RoundRobinArbiter

  RR-Arbiter: Verilog implementation of a fair, rotating grant selector for multiple request sources. Allows equal access to shared resource.

  Language:Verilog3

• govindjeevan/Weighted-Round-Robin-Arbiter

  Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components

  Language:Verilog182

• w18191211897/axi2ahb_bridge

  做一个axi2ahb的转换桥

  1

• KasuganoSoraaa/simple-AXI2AHB-bridge

  AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc

  Language:Verilog3210

• WangXuan95/FPGA-DDR-SDRAM

  An AXI4-based DDR1 controller to realize mass, cheap memory for FPGA. 基于FPGA的DDR1控制器，为低端FPGA嵌入式系统提供廉价、大容量的存储。

  Language:Verilog13828

• donlon/axi-dma-controller

  High Performance AXI4-based Direct Memory Access (DMA) Controller

  Language:SystemVerilog42

• situ-xiao/AXI4-DMA

  Language:Verilog1

• absolutezero2730/AXI_DMA_FIFO

  Transfer data from DDR memory to AXI4-Stream Data FIFO and back through AXI DMA

  Language:VHDL156

• gednyengs/dma

  Open-Source AXI4 DMA Engine in SystemVerilog and Chisel

  Language:Scala74

• ypyp3/uart-axi

  AXI4 bus master, controlled by UART

  Language:SystemVerilog32

• WangXuan95/FPGA-UART

  Include 3 independent modules: UART receiver, UART transmitter, UART to AXI4 master. 包含3个独立模块：UART接收器、UART发送器、UART转AXI4交互式调试器。

  Language:Verilog10422

• ultraembedded/core_dbg_bridge

  UART -> AXI Bridge

  Language:Verilog5417

• GeorgeLin200100/axi_ddr

  DDR4 with AXI4 interface RD & WR test

  Language:VHDL2

• mballance/axi4_ddr3_ctrl

  AXI4 DDR3 Controller written in CHISEL

  1

• PaserTech-Hardware/GowinDDR3_AXI4_SpinalHDL

  Gowin DDR3 Controller with AXI4 Implementation | 高云DDR3内存控制器AXI4接口实现

  Language:Verilog186

• ultraembedded/core_jpeg_decoder

  HW JPEG decoder wrapper with AXI-4 DMA

  Language:Verilog316

• knhitesh/AXI4_FIFO

  Language:SystemVerilog24

• apriya-ram/AXI_FIFO_BFM

  AXI4 with a FIFO integrated with VIP

  Language:SystemVerilog1482

• zombie0117/yolov3-tiny-onnx-TensorRT

  convert your yolov3-tiny model to trt model

  Language:Python9034

• eugene-tarassov/vivado-risc-v

  Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

  Language:Tcl821186

• thedatabusdotio/fpga-ml-accelerator

  This repository hosts the code for an FPGA based accelerator for convolutional neural networks

  Language:Verilog11725

• elliothe/pytorx

  Neural Network Evaluation Tool on Crossbar-based Accelerator with Resistive Memory

  Language:Python3422

• yz27/Optimization-of-energy-efficiency-for-FPGA-based-convolutional-neural-networks-accelerator

  Optimization-of-energy-efficiency-for-FPGA-based-convolutional-neural-networks-accelerator

  1

• Tianyang-Liu0307/Deep-neural-network-accelerator-based-on-Pynq-Z2

  Deep neural network accelerator based on Pynq-Z2

  Language:C++41

• Oracking/FPGA_Accelerator

  Using Commercial FPGAs as Accelerators for Artificial Neural Networks in Embedded Systems

  Language:VHDL41

• matin-yousefzade/Hardware-Accelerator-for-Neural-Networks

  A processing element (PE), that makes two dimensional systolic array for hardware acceleration in neural networks.

  Language:SystemVerilog1

• Jiawei888/FPGA-CNN-Accelerator

  The goal of this design is to use the PYNQ-Z2 development board to design a general convolution neural network accelerator. And through real-time handwritten digits input and MNIST test data set to verify the correctness and accuracy of the system.

  Language:C++96

• OmarBazaraa/DCNN-Accelerator

  Convolution Neural Network Hardware Accelerator

  Language:Verilog22

• jonathan93sh/CNNA

  A generic Convolutional Neural Network (CNN) Accelerator (CNNA) for FPGA

  Language:VHDL215