yangxuchen

yangxuchen's Stars

• OpenROADM/OpenROADM_MSA_Public

  Open ROADM MSA

  6780

• gjghlinix/FPGA-

  FPGA资料文件（不断更新）

  41

• chatgpt-4-mirror-zh/chatgpt-mirror-zh

  本站提供国内访问ChatGPT的免费服务，汇总了多个ChatGPT镜像网站，包括GPT4、AI写作、AI绘图等功能。

  18

• PKU-HunterWu/LDPC-Encoder-Decoder

  基于Matlab的LDPC编解码算法实现及LDPC码性能测试

  Language:MATLAB8013

• alexforencich/verilog-axi

  Verilog AXI components for FPGA implementation

  Language:Verilog1.6k464

• Digilent/vivado-library

  Language:C588320

• ultraembedded/core_dbg_bridge

  UART -> AXI Bridge

  Language:Verilog6017

• ultraembedded/core_dvi_framebuffer

  Minimal DVI / HDMI Framebuffer

  Language:Verilog7812

• WangXuan95/FPGA-UART

  This repo includes 3 independent modules: UART receiver, UART transmitter, UART to AXI4 master. 本项目包含3个独立模块：UART接收器、UART发送器、UART转AXI4交互式调试器。

  Language:Verilog13027

• WangXuan95/FPGA-DDR-SDRAM

  An FPGA-based DDR1 controller. 基于FPGA的DDR1控制器，为低端FPGA嵌入式系统提供廉价、大容量的存储。

  Language:Verilog15634

• www-asics-ws/wb_conmax

  WISHBONE Interconnect

  Language:Verilog115

• ZipCPU/wb2axip

  Bus bridges and other odds and ends

  Language:Verilog503101

• freecores/wb_dma

  WISHBONE DMA/Bridge IP Core

  Language:Verilog185

• ZipCPU/wbscope

  A wishbone controlled scope for FPGA's

  Language:Verilog746

• skristiansson/wb_sdram_ctrl

  SDRAM controller with multiple wishbone slave ports

  Language:Verilog2812

• ZipCPU/wbi2c

  Wishbone controlled I2C controllers

  Language:Verilog4510

• ZipCPU/qspiflash

  A set of Wishbone Controlled SPI Flash Controllers

  Language:Verilog7624

• olofk/wb_intercon

  Wishbone interconnect utilities

  Language:Verilog3813

• mczerski/SD-card-controller

  WISHBONE SD Card Controller IP Core

  Language:Verilog11948

• zhengzhideakang/Verilog--FIFO

  包含同步FIFO，异步FIFO，不同位宽转换

  Language:Verilog5

• zhengzhideakang/Verilog--moving-average

  Verilog功能模块——滑动平均值（使用FIFO）

  Language:Verilog1

• Tommydag/CAN-Bus-Controller

  An CAN bus Controller implemented in Verilog

  Language:Verilog4325

• WangXuan95/FPGA-CAN

  An FPGA-based lightweight CAN bus controller. 基于FPGA的轻量级CAN总线控制器。

  Language:Verilog23569

• freecores/verilog_fixed_point_math_library

  Fixed Point Math Library for Verilog

  Language:Verilog12335

• freecores/dma_axi

  AXI DMA 32 / 64 bits

  Language:Verilog10233

• freecores/8051

  8051 core

  Language:Verilog9933

• hushon/Tiny-RISCV-CPU

  Mini RISC-V CPU

  Language:Verilog93

• risclite/R8051

  8051 soft CPU core. 700-lines statements for 111 instructions . Fully synthesizable Verilog-2001 core.

  Language:Verilog16544

• ajackevic/ELEC3875

  Design and implementation of an AES algorithm on an MATLAB & FPGA

  Language:Verilog6

• ajackevic/ELEC5882

  The Design and Implementation of a Pulse Compression Filter on an FPGA.

  Language:Verilog2512