Issues
- 0
Add global reigsters
#38 opened by yaqiz01 - 0
Predication support in CtrlBox
#34 opened by yaqiz01 - 0
Unparallelized sram load/store
#30 opened by yaqiz01 - 0
Change in PCU CtrlBox
#33 opened by yaqiz01 - 0
Unparalleled dense load and store
#29 opened by yaqiz01 - 0
Inner Unit Pipeline horizontal fusion
#10 opened by yaqiz01 - 0
Bypass Elimination
#3 opened by yaqiz01 - 0
Remove Seq in denseStore in pirgen
#31 opened by yaqiz01 - 0
- 0
Automatic Hierarchy in spade
#28 opened by yaqiz01 - 0
Handle fifo not full signal.
#27 opened by yaqiz01 - 0
Bubble in dense load and store
#26 opened by yaqiz01 - 0
Plasticine Unit Tests
#24 opened by yaqiz01 - 0
Inner loop Sequential
#37 opened by yaqiz01 - 1
- 0
Refactor Delay mapper to post mapping analysis
#35 opened by yaqiz01 - 0
FIFO notEmpty
#32 opened by yaqiz01 - 10
Outer Loop Counterchain copy
#13 opened by yaqiz01 - 2
Route remote done signal in PMU control
#25 opened by yaqiz01 - 0
Consider used register in counter space pruning
#14 opened by yaqiz01 - 0
Outer unit controller vertical fusion
#11 opened by yaqiz01 - 0
- 9
PISA codegen syntax issues
#19 opened by raghup17 - 2
StreamPipe cuA control flow
#22 opened by raghup17 - 0
SimpleTileLoad syntax issues
#23 opened by raghup17 - 0
Handle multiple last stage control
#12 opened by yaqiz01 - 0
Redundant routing in outer controller
#15 opened by yaqiz01 - 1
Control Routing Issue
#18 opened by yaqiz01 - 2
PIR Syntax Questions
#20 opened by dkoeplin - 0
- 0
- 0
Add metadata to PIR
#9 opened by yaqiz01 - 5
PIR Example
#2 opened by yaqiz01 - 0
- 0
Add double buffer swapWrite swapRead Ctrs
#6 opened by yaqiz01 - 0
Generated DotProduct missing dependencies
#7 opened by yaqiz01 - 0
Outer controller merge
#4 opened by yaqiz01 - 2
PIR compute unit syntax/convention questions
#1 opened by dkoeplin