/Multicycle-RISC-Processor

Verilog implementation of 16-bit multi-cycle RISC15 processor design

Primary LanguageTeX

Multicycle RISC15 Processor

Verilog Implementation and Design Specifications of RISC15 processor based on IIT-B-RISC15 ISA done as a part of Microproccesors Course [EE 309 & EE 337] at IIT-Bombay.

Authors

  • Meet Shah | 13D070003
  • Yash Bhalgat | 13D070014
  • Navjot Singh | 130110071

FPGA

ALtera DE0 Nano FPGA