yathAg

Electronics Enthusiast | VLSI | Embedded Systems

Purdue UniversityWest Lafayette

Pinned Repositories

learn-fpga
Learning FPGA, yosys, nextpnr, and RISC-V
Language:C++2.6k 85 74245
OpenROAD-flow-scripts
OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
Language:Verilog349 12 391292
AES_gf180
Language:Verilog00
FemtoRV_RISCV
RISCV32I single core processor with UART implemented on the ARTIX7 FPGA
Language:C01
gem5Project
Language:C++10
openroad_vsd_7nmContest
111
Physical_Verification_SKY130A
Understanding Physical Verification using open source tools such as Magic and Netgen
Language:Verilog8 1 05
projectBucket
10
VSD_HDP
RTL to GDSII for RISC V Core with SRAM
Language:Verilog3 1 01
VSDSquadron
Schematics and images for the VSDSquadron board series, crafted to make RISC-V education accessible and engaging for learners at all levels. This board family is tailored to simplify the learning process, providing a practical, hands-on approach to RISC-V architecture and design principles.
Language:Batchfile00

yathAg's Repositories

yathAg/openroad_vsd_7nmContest
111
yathAg/Physical_Verification_SKY130A
Understanding Physical Verification using open source tools such as Magic and Netgen
Language:Verilog8 1 05
yathAg/VSD_HDP
RTL to GDSII for RISC V Core with SRAM
Language:Verilog3 1 01
yathAg/gem5Project
Language:C++10
yathAg/projectBucket
10
yathAg/Shakti
Codes for the shakti processor
Language:C1 1 01
yathAg/AES_gf180
Language:Verilog00
yathAg/AUVSI_Power_Distribution
Power distribution system for 12S 30A Hex-Rotor propultion System
00
yathAg/binary_watch
Language:C++00
yathAg/FemtoRV_RISCV
RISCV32I single core processor with UART implemented on the ARTIX7 FPGA
Language:C01
yathAg/squadron_lib
00
yathAg/VSDSquadron
Schematics and images for the VSDSquadron board series, crafted to make RISC-V education accessible and engaging for learners at all levels. This board family is tailored to simplify the learning process, providing a practical, hands-on approach to RISC-V architecture and design principles.
Language:Batchfile00
yathAg/ECE51216_sat_solver
Language:Python
yathAg/ECE695MLCC
Language:Python
yathAg/gatsby-portfolio
Language:TypeScript1 0
yathAg/learn-fpga
Learning FPGA, yosys, nextpnr, and RISC-V
Language:C++
yathAg/OpenROAD-flow-scripts
OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
Language:Verilog
yathAg/PUF
Language:Tcl1 0
yathAg/PUF_GF180
Language:Verilog
yathAg/PX4-Autopilot
PX4 Autopilot Software
Language:C++
yathAg/raspberryPi_setup
yathAg/sky130test
Language:Verilog
yathAg/STM32_Shield
STM32 Nucleo Shields for CAN and RS485
yathAg/Swadeshi_Microprocessor_Challenge
Smart ASRS Sytem Using Shakti RISCV Processor
yathAg/Synopsys_RTL2GDSII_SFAL
Language:Verilog
yathAg/time
time library for shakti sdk
Language:C
yathAg/VSDSquadron_AI
yathAg/VSDSquadron_FM
Code for VSDSquadron_FM
Language:C
yathAg/workflow_scripts
Collection of scripts to aid day to day work
Language:Python