/Single-Cycle-CPU-with-Verilog

Primary LanguageVerilog

Single Cycle MIPS CPU with Verilog

This is a course project of Digital Circuit and CPU course of Department of EE., Tsinghua University.

file list

  • code_1/ : original code provided by teaching assistant
  • code_2/ : modified code
  • questions.pdf : the document of this project, in which you can find which files are required to be modified
  • report.pdf : the final commit report of this project, including answers of questions and implementation details.