Pinned Repositories
1bit_precoding
a2i
ac_types
Algorithmic C Datatypes
FreeRTOS_on_SweRV
Test simulation environment to run FreeRTOS using WD SweRV processor
jtag_dpi
LimeSDRTest
LS_MMSE_channel_estimator_for_OFDM
LTE-OFDM-SYSTEM
Simulates an entire Transmission, Channel and Receiver chain for LTE OFDM system in Matlab
MIMO-OFDM
MATLAB code simulating different MIMO-OFDM schemes
xilinx_iic_hw_ctrl
ycyang0508's Repositories
ycyang0508/LimeSDRTest
ycyang0508/xilinx_iic_hw_ctrl
ycyang0508/async_FIFO
This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is coded by me(Xianghzi Meng)
ycyang0508/axi
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
ycyang0508/eth_vlg
ycyang0508/gen_amba_2021
AMBA bus generator including AXI4, AXI3, AHB, and APB
ycyang0508/OpenFPGA
An Open-source FPGA IP Generator
ycyang0508/OpenUSRP
using LimeSDR to simulate USRP B210
ycyang0508/airisc_core_complex
Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional periperals.
ycyang0508/awesome-opensource-asic-resources
ycyang0508/bt_modem
ycyang0508/cosim_bfm_library
HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI
ycyang0508/CycloneTCP
Dual IPv4/IPv6 Stack
ycyang0508/DPI_socket
ycyang0508/gen_amba
AMBA bus generator including AXI, AHB, and APB
ycyang0508/Git-Tutorials
Git-Tutorials GIT基本使用教學:memo:
ycyang0508/gvsoc
Pulp virtual platform
ycyang0508/impacket
Impacket is a collection of Python classes for working with network protocols.
ycyang0508/ipxact2systemverilog
Translates IPXACT XML to synthesizable VHDL or SystemVerilog
ycyang0508/obudpst
OB-UDPST is a client/server utility to do UDP-based IP capacity measurements (see TR-471 for details).
ycyang0508/PeakRDL-regblock
Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
ycyang0508/PlutoSDR_tone_swep
ycyang0508/Rev-Soc
ycyang0508/RISC-V-TLM
RISC-V SystemC-TLM simulator
ycyang0508/Shunt
SystemVerilog DPI "TCP/IP Shunt" (TCP/IP system verilog socket library)
ycyang0508/srdl2sv
A SystemRDL 2.0 to (synthesizable) SystemVerilog compiler.
ycyang0508/style-guides
lowRISC Style Guides
ycyang0508/verible
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, and formatter.
ycyang0508/wirehair
Wirehair : O(N) Fountain Code for Large Data
ycyang0508/xgpon
XG-PON Simulation Module for NS-3