yellowtaoworkshop's Stars
Archmage83/tvapk
收集各大AndroidTV的apk应用,可免费看vip和国外电影电视。如大家有也可以贡献一下。
chipsalliance/verible
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
nitronis/UVM
Mirrors of the Accellera UVM Reference Implementations at https://www.accellera.org/downloads/standards/uvm.
gmlarumbe/tree-sitter-systemverilog
Rewrite of tree-sitter-verilog
gmlarumbe/verilog-ext
Verilog Extensions for Emacs
fvutils/pyvsc
Python packages providing a library for Verification Stimulus and Coverage
beeender/glrnvim
glrnvim wraps nvim with your favourite terminal into a standalone, non-fancy but daily-usable neovim GUI.
subbdue/systemverilog.io
Code used in
suisuisi/SystemVerilog
SystemVerilog of syntax and Practices
mikeroyal/Verilog-SystemVerilog-Guide
Verilog/SystemVerilog Guide
fastapi/typer
Typer, build great CLIs. Easy to code. Based on Python type hints.
topjohnwu/Magisk
The Magic Mask for Android
salvogiangri/KnoxPatch
LSPosed module to get Samsung apps/features working again in your rooted Galaxy device.
openhwgroup/core-v-verif
Functional verification project for the CORE-V family of RISC-V cores.
themkat/.emacs.d
My .emacs.d configuration. Even have a Github Actions pipeline :smirk:
alexafish/RegAnalyzer64
Register Analyzer 64bit
GeneKao/oh-my-phd
Oh My PhD!
GeneKao/orgmode-latex-templates
My org-mode starter codes for exporting to latex/pdf
google/zx
A tool for writing better scripts
chenxqiyu/opencore_i5_9400f_b365m_pixiu
andyninety9/Hackintosh-CoffeeLake-B365M-RX570-OpenCore
Hackintosh macOS Ventura 13.2.1 in MSI B365M Pro-VH + Intel Core I3-9100F + Gigabyte Radeon RX 570
lowRISC/ibex
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
ucb-bar/chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
Anduin2017/HowToCook
程序员在家做饭方法指南。Programmer's guide about how to cook at home (Simplified Chinese only).
alice820621/SystemVerilog-Implementation-of-DDR3-Controller
The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a predefined DDR3 memory. Successful design verification is achieved via a specialized test bench and connected to provided AHB by a SystemVerilog interface.
funannoka/SoC-Design-DDR3-Controller
DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog
fronttang/ASUS_PRIME_B365M-A_Hacintosh
ASUS PRIME B365M-A Hacintosh
bollwarm/perlonelinecn
Perl 单行解释中文版