yfleo's Stars
esnet/esnet-smartnic-hw
ESnet SmartNIC hardware design repository.
Xilinx/pcie_qdma_ats_example
Xilinx/xup_fpga_vivado_flow
AMD Xilinx University Program Vivado tutorial
Xilinx/open-nic
AMD OpenNIC Project Overview
Xilinx/Alveo-PYNQ
Introductory examples for using PYNQ with Alveo
Xilinx/AlveoLink
This repository contains IPs, Vitis kernels and software APIs that can be leveraged by Vitis users to build scale-out solutions on multiple Alveo cards.
Xilinx/Vitis-Tutorials
Vitis In-Depth Tutorials
fpgasystems/fpga-network-stack
Scalable Network Stack for FPGAs (TCP/IP, RoCEv2)
Xilinx/dma_ip_drivers
Xilinx QDMA IP Drivers
NetFPGA/netfpga
NetFPGA 1G infrastructure and gateware
NetFPGA/NetFPGA-public
NetFPGA public repository
alexforencich/verilog-cam
Verilog Content Addressable Memory Module
mcjtag/tcam
TCAM (Ternary Content-Addressable Memory) in Verilog
gengyl08/NetFPGA-10G
Yilong's NetFPGA-10G Repo
ucsdsysnet/corundum
Open source FPGA-based NIC and platform for in-network compute
alexforencich/verilog-ethernet
Verilog Ethernet components for FPGA implementation
shuckc/verilog-utils
native Verilog pcap, littletoe, bcd, xml and hash modules, with Icarus testbenches
CoreyChen922/sata3_host_controller
It is SATA 3 host controller. Using this you can read write to sata3 sdd/hdd from your fpga logic with simple memory like interface.
0x3f3f3f3f/Satania-QQBot
萨塔妮娅 Project —— QQ机器人
CoreyChen922/sata_2_host_controller
Sata 2 Host Controller for FPGA implementation
Elphel/x393_sata
mirror of https://git.elphel.com/Elphel/x393_sata
LeiWang1999/FPGA
帮助大家进行FPGA的入门,分享FPGA相关的优秀文章,优秀项目
torvalds/linux
Linux kernel source tree
DPDK/dpdk
Data Plane Development Kit
eastmountyxz/ImageProcessing-Python
该资源为作者在CSDN的撰写Python图像处理文章的支撑,主要是Python实现图像处理、图像识别、图像分类等算法代码实现,希望该资源对您有所帮助,一起加油。
linux-rdma/rdma-core
RDMA core userspace libraries and daemons
invernizzi/scapy-http
Support for HTTP in Scapy
jjqqkk/jjqqkk
JJQQKK上网助手
Elphel/eddr3
mirror of https://git.elphel.com/Elphel/eddr3
gvsrmk/Design-and-Verification-of-DDR3-SDRAM-memory-controller
Designed a closed page policy memory controller following the timing specifications for DDR3 DRAM in system verilog. Was responsible for setting up the interfaces and writing tasks for various operations. Performed randomized, Constrained, and directed test cases to validate our DUT.