yfleo

yfleo's Stars

• esnet/esnet-smartnic-hw

  ESnet SmartNIC hardware design repository.

  Language:SystemVerilog394

• Xilinx/pcie_qdma_ats_example

  Language:Verilog185

• Xilinx/xup_fpga_vivado_flow

  AMD Xilinx University Program Vivado tutorial

  Language:Verilog2612

• Xilinx/open-nic

  AMD OpenNIC Project Overview

  Language:Shell21737

• Xilinx/Alveo-PYNQ

  Introductory examples for using PYNQ with Alveo

  Language:Jupyter Notebook4717

• Xilinx/AlveoLink

  This repository contains IPs, Vitis kernels and software APIs that can be leveraged by Vitis users to build scale-out solutions on multiple Alveo cards.

  Language:Verilog194

• Xilinx/Vitis-Tutorials

  Vitis In-Depth Tutorials

  Language:C1.2k549

• fpgasystems/fpga-network-stack

  Scalable Network Stack for FPGAs (TCP/IP, RoCEv2)

  Language:C++729259

• Xilinx/dma_ip_drivers

  Xilinx QDMA IP Drivers

  Language:C550411

• NetFPGA/netfpga

  NetFPGA 1G infrastructure and gateware

  Language:Verilog364141

• NetFPGA/NetFPGA-public

  NetFPGA public repository

  177129

• alexforencich/verilog-cam

  Verilog Content Addressable Memory Module

  Language:Verilog9846

• mcjtag/tcam

  TCAM (Ternary Content-Addressable Memory) in Verilog

  Language:Verilog398

• gengyl08/NetFPGA-10G

  Yilong's NetFPGA-10G Repo

  Language:Verilog1030

• ucsdsysnet/corundum

  Open source FPGA-based NIC and platform for in-network compute

  Language:Verilog17145

• alexforencich/verilog-ethernet

  Verilog Ethernet components for FPGA implementation

  Language:Verilog2.2k668

• shuckc/verilog-utils

  native Verilog pcap, littletoe, bcd, xml and hash modules, with Icarus testbenches

  Language:Verilog4120

• CoreyChen922/sata3_host_controller

  It is SATA 3 host controller. Using this you can read write to sata3 sdd/hdd from your fpga logic with simple memory like interface.

  Language:Verilog6048

• 0x3f3f3f3f/Satania-QQBot

  萨塔妮娅 Project —— QQ机器人

  Language:JavaScript11621

• CoreyChen922/sata_2_host_controller

  Sata 2 Host Controller for FPGA implementation

  Language:Verilog1323

• Elphel/x393_sata

  mirror of https://git.elphel.com/Elphel/x393_sata

  Language:Verilog3318

• LeiWang1999/FPGA

  帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目

  3.8k653

• torvalds/linux

  Linux kernel source tree

  Language:C178k53.1k

• DPDK/dpdk

  Data Plane Development Kit

  Language:C3.3k1.2k

• eastmountyxz/ImageProcessing-Python

  该资源为作者在CSDN的撰写Python图像处理文章的支撑，主要是Python实现图像处理、图像识别、图像分类等算法代码实现，希望该资源对您有所帮助，一起加油。

  Language:Jupyter Notebook1.8k447

• linux-rdma/rdma-core

  RDMA core userspace libraries and daemons

  Language:C1.5k674

• invernizzi/scapy-http

  Support for HTTP in Scapy

  Language:Python30177

• jjqqkk/jjqqkk

  JJQQKK上网助手

  518134

• Elphel/eddr3

  mirror of https://git.elphel.com/Elphel/eddr3

  Language:Verilog4017

• gvsrmk/Design-and-Verification-of-DDR3-SDRAM-memory-controller

  Designed a closed page policy memory controller following the timing specifications for DDR3 DRAM in system verilog. Was responsible for setting up the interfaces and writing tasks for various operations. Performed randomized, Constrained, and directed test cases to validate our DUT.

  Language:SystemVerilog61