Pinned Repositories
2dconv-FPGA
A 2D convolution hardware implementation written in Verilog
3DCNN
3D convolutional neural network for video classification
8bit_datapath_AES
This is a 8-bit datapath hardware implementation of AES.
AutoSA
AutoSA: Polyhedral-Based Systolic Array Compiler
blockchainacceleration
fccm2021-tutorial
FCCM 2021 Tutorial: FPGA High-Level Synthesis: Good Practices for Quality and Productivity
tvm
Open deep learning compiler stack for cpu, gpu and specialized accelerators
tvm-vta
Open, Modular, Deep Learning Accelerator
ultra_net
FPGA-based neural network inference project for 2020 DAC System Design Contest
yluo39github's Repositories
yluo39github/AutoSA
AutoSA: Polyhedral-Based Systolic Array Compiler
yluo39github/blockchainacceleration
yluo39github/fccm2021-tutorial
FCCM 2021 Tutorial: FPGA High-Level Synthesis: Good Practices for Quality and Productivity
yluo39github/tvm
Open deep learning compiler stack for cpu, gpu and specialized accelerators
yluo39github/tvm-vta
Open, Modular, Deep Learning Accelerator
yluo39github/awesome-domain-adaptation
A collection of AWESOME things about domian adaptation
yluo39github/chisel3
Chisel 3: A Modern Hardware Design Language
yluo39github/Coyote
Framework providing operating system abstractions and a range of shared networking (RDMA, TCP/IP) and memory services to common modern heterogeneous platforms.
yluo39github/cuFHE
CUDA-accelerated Fully Homomorphic Encryption Library
yluo39github/Deep_Dup_A
yluo39github/DEEPDUPA
yluo39github/deepmind-research
This repository contains implementations and illustrative code to accompany DeepMind publications
yluo39github/DualStyleGAN
[CVPR 2022] Pastiche Master: Exemplar-Based High-Resolution Portrait Style Transfer
yluo39github/ethminer
Ethereum miner with OpenCL, CUDA and stratum support
yluo39github/examples
A set of examples around pytorch in Vision, Text, Reinforcement Learning, etc.
yluo39github/EzPC
yluo39github/FedML
FedML - The federated learning and distributed training library enabling machine learning anywhere at any scale. It's backed by FedML, Inc (https://FedML.ai). Supporting large-scale geo-distributed training, cross-device federated learning on smartphones/IoTs, cross-silo federated learning on data silos, and research simulation. Best Paper Award at NeurIPS
yluo39github/fucking-algorithm
刷算法全靠套路，认准 labuladong 就够了！English version supported! Crack LeetCode, not only how, but also why.
yluo39github/gold-miner
🥇掘金翻译计划，可能是世界最大最好的英译中技术社区，最懂读者和译者的翻译平台：
yluo39github/homepage
yluo39github/LeetCode-Go
✅ Solutions to LeetCode by Go, 100% test coverage, runtime beats 100% / LeetCode 题解
yluo39github/LeNet_HLS_on_PYNQ
yluo39github/nufhe
NuCypher fully homomorphic encryption (NuFHE) library implemented in Python
yluo39github/pp4fpgas-cn
中文版 Parallel Programming for FPGAs
yluo39github/PyTorch-GAN
PyTorch implementations of Generative Adversarial Networks.
yluo39github/RapidStream
[FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.
yluo39github/Real-Time-Rendering-4th-Bibliography-Collection
Real-Time Rendering 4th (RTR4) 参考文献合集典藏 | Collection of <Real-Time Rendering 4th (RTR4)> Bibliography / Reference
yluo39github/tapa
Join our FCCM 2022 Tutorial on May 18th! TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerators.
yluo39github/the-gan-zoo
A list of all named GANs!
yluo39github/zynq_tdc
A fast high-resolution time-to-digital converter in the Red Pitaya Zynq-7010 SoC