Pinned Repositories
DirectNVM
An open-source RTL NVMe controller IP for Xilinx FPGA.
dram_sim_model
A Xilinx DDR3 simulation model wrapper logic.
LRUCache
Set-associative cache using pseudo bit-LRU replacement policy, written in C++ and sythesized with Vivado HLS.
rtl_template
A template folder for Vivado RTL project, including .gitignore.
SudokuSolver
yu-zou's Repositories
yu-zou/DirectNVM
An open-source RTL NVMe controller IP for Xilinx FPGA.
yu-zou/dram_sim_model
A Xilinx DDR3 simulation model wrapper logic.
yu-zou/LRUCache
Set-associative cache using pseudo bit-LRU replacement policy, written in C++ and sythesized with Vivado HLS.
yu-zou/rtl_template
A template folder for Vivado RTL project, including .gitignore.
yu-zou/SudokuSolver
yu-zou/alpine-vim
"dockerized" Vim
yu-zou/blog-image-repo
yu-zou/CatSlaveSaver
Ball pick-up robot to save your life when playing with your cat.
yu-zou/cppsiphash
SipHash C++11 header-only library
yu-zou/CTREncryption
Cache-enabled counter encryption, written in Vivado HLS.
yu-zou/dockerized-vim
yu-zou/drawio
draw.io is a JavaScript, client-side editor for general diagramming and whiteboarding
yu-zou/fpga-drive-aximm-pcie
Example designs for FPGA Drive FMC
yu-zou/getgist
🖥️ Easily download any file from a GitHub Gist, with one single command.
yu-zou/hexo-theme-Wikitten
A theme of Hexo for Wiki seem like Wikitten style.
yu-zou/hls_template
A template folder for Vivado HLS project including .gitignore.
yu-zou/nanoGPT
The simplest, fastest repository for training/finetuning medium-sized GPTs.
yu-zou/non-stencil-loop-benchmarks
Benchmarks used in our FPGA'19 paper
yu-zou/pyxsi
Python/C/RTL cosimulation with Xilinx's xsim simulator
yu-zou/rosetta
Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs
yu-zou/siphash-verilog
Verilog implementation of pipelined 64-bit SipHash2-4 hash function
yu-zou/tiny-gpu
A minimal GPU design in Verilog to learn how GPUs work from the ground up
yu-zou/verible
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
yu-zou/vitis-mre
Minimal reproducible example.
yu-zou/vtr-verilog-to-routing
Verilog to Routing -- Open Source CAD Flow for FPGA Research
yu-zou/yu-zou
yu-zou/zhenye-na
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