This repository contains the riscvOVPsimCOREV simulator which provides a reference of the OpenHW Group CORE-V processor cores.
Each version of the release is provided in a separate branch which corresponds to the release version.
The latest release version is v20231026
riscvOVPsimCOREV is the free RISC-V ISS (Instruction Set Simulator) for CORE-V developers in the OpenHW ecosystem, and is based on the leading RISC-V simulation technology from Imperas together with the reference models of the OpenHW CORE-V IP portfolio. An ISS targeted for software development provides a programmers view of the key hardware features of the processor. However, this use case is fundamentally different to the requirements of hardware verification, for details of the OpenHW functional verification project and reference model, please see the core-v-verif repository.
riscvOVPsimCOREV can be configured for the complete range of the OpenHW CORE V processor IP portfolio including:
- CV32E40P
- CV32E40P-MCU
- CV32E40Pv2
- CV32E41P
- CV32E40S
- CV32E40X
- CV32E20
- CV32A5
- CV32A6
- CV64A6
The capabilities of these models are closely aligned with the deliverables and maturity of the respective core projects, more information on the features and functionality are available in the OpenHW Group project repositories on GitHub.
This README is a summary overview of riscvOVPsimCOREV, for more detailed information see the riscvOVPsimCOREV user guide.