This RISC-V implementation is described in the book "Inside An Open-Source Processor" ISBN 978-3-89576-443-1
yuri-panchul/yrv-plus
Verilog implementation of RISC-V: RV32IAC plus much of B. 32-bit or 16-bit bus.
VerilogApache-2.0
Verilog implementation of RISC-V: RV32IAC plus much of B. 32-bit or 16-bit bus.
VerilogApache-2.0