yutyan0119's Stars
qemu/qemu
Official QEMU mirror. Please see https://www.qemu.org/contribute/ for how to submit changes to QEMU. Pull Requests are ignored. Please only use release tarballs from the QEMU website.
nuta/resea
A microkernel-based hackable operating system.
ytoyoyama/interface_trykernel
Interface 2023年7月号 特集「ゼロから作るOS」配布プログラム
VerificationExcellence/SystemVerilogReference
training labs and examples
Obijuan/open-fpga-verilog-tutorial
Learn how to design digital systems and synthesize them into an FPGA using only opensource tools
seldridge/verilog
Repository for basic (and not so basic) Verilog blocks with high re-use potential
takahirox/riscv-rust
RISC-V processor emulator written in Rust+WASM
Argyle-Software/kyber
A rust implementation of the Kyber post-quantum KEM
vista-simulator/vista
Data-driven simulation for training and evaluating full-scale autonomous vehicles.
Alignof/carron
rv32/64imac emulator
atulmahind/PEKS
Implementation of Public Key Encryption with Keyword Search
gopher-os/gopher-os
A proof of concept OS kernel written in Go
o-oconnell/minixfromscratch
Development and compilation setup for the book versions of MINIX (2.0.0 and 3.1.0) on QEMU
ahmedbahaaeldin/From-0-to-Research-Scientist-resources-guide
Detailed and tailored guide for undergraduate students or anybody want to dig deep into the field of AI with solid foundation.
Valkyrja3607/tuning_playbook_ja
ディープラーニングモデルの性能を体系的に最大化するためのプレイブック
ApolloAuto/apollo
An open autonomous driving platform
trabucayre/openFPGALoader
Universal utility for programming FPGA
starfive-tech/VisionFive2
mit-pdos/xv6-riscv
Xv6 for RISC-V
sifive/elf2hex
Converts ELF files to HEX files that are suitable for Verilog's readmemh.
peterbraden/genetic-lisa
An art project to generate the mona-lisa with a genetic algorithm.
riscv-software-src/riscv-tests
ciniml/seccamp_2022_riscv_cpu
セキュリティキャンプ 2022 Y4 RISC-V CPU自作ゼミ 講義資料
rutan/togelack
Slackまとめ
ridecore/ridecore
RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.
phil-opp/blog_os
Writing an OS in Rust
asfdrwe/ASFRV32IM-super
Single Cycle In-Order SuperScalar RISC-V RV32IM implementations
stnolting/neorv32
:desktop_computer: A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
dininduwm/RV32IM-pipeline-implementation
risclite/rv32m-multiplier-and-divider
a multiplier÷r verilog RTL file for RV32M instructions