Pinned Repositories
aes128-hdl
A high-throughput VHDL and SystemVerilog implementation of AES-128 including scripts for a full front-end design process.
cordic
An implementation of the CORDIC algorithm in Verilog.
CPlusPlusThings
C++那些事
dpu_on_zcu102
The Guidance For Installing dpu and some other stuff On Xilinx ZCU102
FPGA_SM4
FPGA implementation of Chinese SM4 encryption algorithm.
HashCalculator
Helper tool to calculate hashes of data
KCFcpp
C++ Implementation of KCF Tracker
keras-yolo3
A Keras implementation of YOLOv3 (Tensorflow backend)
md5_core
MD5 core in verilog
modbus_crc_verilog
FPGA纯逻辑实现modbus通信
yw19e14's Repositories
yw19e14/aes128-hdl
A high-throughput VHDL and SystemVerilog implementation of AES-128 including scripts for a full front-end design process.
yw19e14/cordic
An implementation of the CORDIC algorithm in Verilog.
yw19e14/CPlusPlusThings
C++那些事
yw19e14/dpu_on_zcu102
The Guidance For Installing dpu and some other stuff On Xilinx ZCU102
yw19e14/FPGA_SM4
FPGA implementation of Chinese SM4 encryption algorithm.
yw19e14/HashCalculator
Helper tool to calculate hashes of data
yw19e14/KCFcpp
C++ Implementation of KCF Tracker
yw19e14/keras-yolo3
A Keras implementation of YOLOv3 (Tensorflow backend)
yw19e14/md5_core
MD5 core in verilog
yw19e14/modbus_crc_verilog
FPGA纯逻辑实现modbus通信
yw19e14/Python-100-Days
Python - 100天从新手到大师
yw19e14/resnet_py
Datasets, Transforms and Models specific to Computer Vision
yw19e14/SHA2_Pipelined
yw19e14/sha512
Verilog implementation of the SHA-512 hash function.
yw19e14/SM3_core
yw19e14/verilog-sha256
Implementation of the SHA256 Algorithm in Verilog
yw19e14/Visual-Tracking-Development
Visual Object Tracking
yw19e14/Vitis-AI
Vitis AI is Xilinx’s development stack for AI inference on Xilinx hardware platforms, including both edge devices and Alveo cards.
yw19e14/WANG
DPU-Xilinx-log
yw19e14/xilinx_axidma
A zero-copy Linux driver and a userspace interface library for Xilinx's AXI DMA and VDMA IP blocks. These serve as bridges for communication between the processing system and FPGA programmable logic fabric, through one of the DMA ports on the Zynq processing system. Distributed under the MIT License.
yw19e14/yolov3
YOLOv3 in PyTorch > ONNX > CoreML > TFLite
yw19e14/ZYNQ
⚙️ 基于 Zynq-7 全可编程 SoC 的设计