zchamski

Member of @openhwgroup, expert in SW tools for system performance and efficiency.

Thales

Pinned Repositories

core-v-verif
Functional verification project for the CORE-V family of RISC-V cores.
Language:Assembly421 47 501218
cva6
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
Language:Assembly2.2k 91 1k670
core-v-verif
Functional verification project for the CORE-V family of RISC-V cores.
Language:Assembly0 0 00
cva6
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
Language:Assembly0 0 00
cva6-tools
Toolchain generator for the CORE-V CVA6 family of RISC-V cores
Language:Shell0 2 00
pyelftools
Parsing ELF and DWARF in Python - with RISC-V support
Language:Python0 0 00
riscv-isa-sim
Spike, a RISC-V ISA Simulator
Language:C0 0 00
verilator
Verilator open-source SystemVerilog simulator and lint system
Language:C++00

zchamski's Repositories

zchamski/core-v-verif
Functional verification project for the CORE-V family of RISC-V cores.
Language:Assembly0 0 00
zchamski/cva6
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
Language:Assembly0 0 00
zchamski/cva6-tools
Toolchain generator for the CORE-V CVA6 family of RISC-V cores
Language:Shell0 2 00
zchamski/pyelftools
Parsing ELF and DWARF in Python - with RISC-V support
Language:Python0 0 00
zchamski/riscv-isa-sim
Spike, a RISC-V ISA Simulator
Language:C0 0 00
zchamski/verilator
Verilator open-source SystemVerilog simulator and lint system
Language:C++00