Pinned Repositories
1G_CML_OpenFlow
OpenFlow switch for NetFPGA 1G CML
a-week-in-wild-ai
360 view on ai/ml/dl applications
aes
Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.
Algorithmia
Algorithm and data-structure library for .NET 4.5.2+/Netstandard 2.0+. Algorithmia contains sophisticated algorithms and data-structures like graphs, priority queues, command, undo-redo and more.
anycore-riscv
The AnyCore toolset targetting the RISC-V ISA
anycore-riscv-src
The RTL source for AnyCore RISC-V
awesome-smartnic
A curated list of awesome smartnic tutorials, papers and projects.
FogTorchPI
A probabilistic prototype for deployment of Fog applications.
fpgadev
Development your FPGA accelerator on SmartNIC
NetworkOS
zewei's Repositories
zewei/fpgadev
Development your FPGA accelerator on SmartNIC
zewei/a-week-in-wild-ai
360 view on ai/ml/dl applications
zewei/aes
Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.
zewei/Algorithmia
Algorithm and data-structure library for .NET 4.5.2+/Netstandard 2.0+. Algorithmia contains sophisticated algorithms and data-structures like graphs, priority queues, command, undo-redo and more.
zewei/anycore-riscv-src
The RTL source for AnyCore RISC-V
zewei/awesome-smartnic
A curated list of awesome smartnic tutorials, papers and projects.
zewei/basejump_stl
BaseJump STL: A Standard Template Library for SystemVerilog
zewei/basejump_stl_cornell
Our clone of https://github.com/bespoke-silicon-group/basejump_stl
zewei/beaglev
zewei/Computer-Science-Textbooks
Collect some CS textbooks for learning.
zewei/Cores-SweRV-EH1
SweRV EH1 core
zewei/Cores-SweRV-EH2
zewei/E203plus
upgrade to e203 (a risc-v core)
zewei/fpga-zynq
Support for Rocket Chip on Zynq FPGAs
zewei/INC-ondemand
The Case For In-Network Computing On-Demand, EuroSys 2019
zewei/Main
Main page
zewei/openc910
OpenXuantie - OpenC910 Core
zewei/p4-guide
Guide to p4lang repositories and some other public info about P4
zewei/parallella-riscv
RISC-V port to Parallella Board
zewei/picorv32
PicoRV32 - A Size-Optimized RISC-V CPU
zewei/prog_dataplane_reading_list
The Programmable Data Plane: Reading List
zewei/pspin
PsPIN: A RISC-V in-network accelerator for flexible high-performance low-power packet processing
zewei/RecoNIC
RecoNIC is a software/hardware shell used to enable network-attached processing within an RDMA-featured SmartNIC for scale-out computing.
zewei/riscv-dv
SV/UVM based instruction generator for RISC-V processor verification
zewei/scapytain
Scapytain is a web application that enables you to store, organise and run test campaigns on top of Scapy.
zewei/VG_RTL
All RTL codes of VG project
zewei/VG_Specification
All specifications of VG project
zewei/vivado-build-system
Vivado build system
zewei/vortex
zewei/zdma
Data transport between PL and PS on Xilinx ZYNQ -- MSc Thesis at TUC