In the scope of this project, it is required to design a sequential circuit for a simple two-sided telephone conversation and implement it using Verilog HDL. Then, Simulation is performed and its functional correctness is shown by using Xilinx ISE tool. Basically, the caller initiates a telephone conversation with the callee and the caller sends characters to the callee (and vice versa). The circuit calculates the cost of the call and send the cost value and the characters (sent from the caller to callee and vice versa) as outputs.
There are 8 inputs to the system and 2 outputs are taken at the end of the conversation.
For this, there are 6 different states as it is shown in the state diagram. The details of the implementation can be found in the project report.