Pinned Repositories
adv_dbg_if
Advanced Debug Interface
apb
APB Logic
apb2per
apb_adv_timer
Advanced timer with APB interface
apb_event_unit
apb_gpio
apb_i2c
apb_interrupt_cntrl
Small and simple APB interrupt controller
apb_node
apb_pulpino
zhanggd's Repositories
zhanggd/apb
APB Logic
zhanggd/apb_gpio
zhanggd/apb_node
zhanggd/ariane
Ariane is a 6-stage RISC-V CPU capable of booting Linux
zhanggd/axi
AXI4 and AXI4-Lite interface definitions and testbench utilities
zhanggd/axi2apb
zhanggd/axi_mem_if
Simple single-port AXI memory interface
zhanggd/axi_node
AXI X-Bar
zhanggd/axi_slice
Pipelines the AXI path with FIFOs
zhanggd/axi_slice_dc
AXI Dual-Clock FIFO for clock domain crossings (CDC)
zhanggd/chisel3
Chisel 3
zhanggd/fpga-support
IP Blocks to Support Design, Prototyping, and Verification of PULP on FPGAs
zhanggd/fpu
zhanggd/IPApproX
Set of IP management tools used within the context of the PULP project
zhanggd/pulp-riscv-binutils-gdb
zhanggd/pulp-riscv-gcc
zhanggd/pulp-tools
zhanggd/pulpino
An open-source microcontroller system based on RISC-V
zhanggd/pulpissimo
This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.
zhanggd/riscv
RISCY is an in-order 4-stage RISC-V RV32IMFCXpulp CPU
zhanggd/riscv-fesvr
RISC-V Frontend Server
zhanggd/riscv-gnu-toolchain
GNU toolchain for RISC-V, including GCC
zhanggd/riscv-isa-sim
Spike, a RISC-V ISA Simulator
zhanggd/riscv-opcodes
RISC-V Opcodes
zhanggd/riscv-openocd
Fork of OpenOCD that has RISC-V support
zhanggd/riscv-tests
zhanggd/riscv-tools
RISC-V Tools (GNU Toolchain, ISA Simulator, Tests)
zhanggd/riscv-torture
RISC-V Torture Test
zhanggd/rocket-chip
Rocket Chip Generator
zhanggd/zero-riscy